Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2960359 [patent_doc_number] => 05273912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/921010 [patent_app_country] => US [patent_app_date] => 1992-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2090 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/273/05273912.pdf [firstpage_image] =>[orig_patent_app_number] => 921010 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/921010
Method for manufacturing semiconductor device Jul 27, 1992 Issued
07/917847 MANUFACTURING METHOD FOR SEMICONDUCTOR DEPOSITING DEVICE Jul 22, 1992 Abandoned
Array ( [id] => 3007235 [patent_doc_number] => 05275961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Method of forming insulated gate field-effect transistors' [patent_app_type] => 1 [patent_app_number] => 7/915036 [patent_app_country] => US [patent_app_date] => 1992-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 99 [patent_no_of_words] => 26262 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/275/05275961.pdf [firstpage_image] =>[orig_patent_app_number] => 915036 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/915036
Method of forming insulated gate field-effect transistors Jul 15, 1992 Issued
07/913600 1/F NOISE REDUCTION IN HETEROJUNCTION BIPOLAR TRANSISTORS Jul 12, 1992 Abandoned
Array ( [id] => 3043279 [patent_doc_number] => 05286662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Method for manufacturing field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/912732 [patent_app_country] => US [patent_app_date] => 1992-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2130 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/286/05286662.pdf [firstpage_image] =>[orig_patent_app_number] => 912732 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/912732
Method for manufacturing field effect transistor Jul 12, 1992 Issued
Array ( [id] => 3006710 [patent_doc_number] => 05330933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-19 [patent_title] => 'Method for fabricating semiconductor circuits' [patent_app_type] => 1 [patent_app_number] => 7/911975 [patent_app_country] => US [patent_app_date] => 1992-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2836 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/330/05330933.pdf [firstpage_image] =>[orig_patent_app_number] => 911975 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/911975
Method for fabricating semiconductor circuits Jul 9, 1992 Issued
Array ( [id] => 2958021 [patent_doc_number] => 05198376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Method of forming high performance lateral PNP transistor with buried base contact' [patent_app_type] => 1 [patent_app_number] => 7/909938 [patent_app_country] => US [patent_app_date] => 1992-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2043 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198376.pdf [firstpage_image] =>[orig_patent_app_number] => 909938 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/909938
Method of forming high performance lateral PNP transistor with buried base contact Jul 6, 1992 Issued
Array ( [id] => 2989188 [patent_doc_number] => 05346844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Method for fabricating semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/907068 [patent_app_country] => US [patent_app_date] => 1992-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4515 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/346/05346844.pdf [firstpage_image] =>[orig_patent_app_number] => 907068 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/907068
Method for fabricating semiconductor memory device Jun 29, 1992 Issued
Array ( [id] => 3091529 [patent_doc_number] => 05290718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Simplified high reliability gate oxide process' [patent_app_type] => 1 [patent_app_number] => 7/905772 [patent_app_country] => US [patent_app_date] => 1992-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 7133 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/290/05290718.pdf [firstpage_image] =>[orig_patent_app_number] => 905772 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/905772
Simplified high reliability gate oxide process Jun 28, 1992 Issued
Array ( [id] => 2884841 [patent_doc_number] => 05213989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Method for forming a grown bipolar electrode contact using a sidewall seed' [patent_app_type] => 1 [patent_app_number] => 7/903300 [patent_app_country] => US [patent_app_date] => 1992-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/213/05213989.pdf [firstpage_image] =>[orig_patent_app_number] => 903300 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/903300
Method for forming a grown bipolar electrode contact using a sidewall seed Jun 23, 1992 Issued
07/901032 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING AN INSULATING SIDE WALL Jun 18, 1992 Abandoned
Array ( [id] => 2909399 [patent_doc_number] => 05227321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method for forming MOS transistors' [patent_app_type] => 1 [patent_app_number] => 7/899830 [patent_app_country] => US [patent_app_date] => 1992-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 1687 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227321.pdf [firstpage_image] =>[orig_patent_app_number] => 899830 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/899830
Method for forming MOS transistors Jun 14, 1992 Issued
07/898196 FABRICATION PROCESS FOR SCHOTTKY DIODE WITH LOCALIZED PRODE WELL Jun 11, 1992 Issued
Array ( [id] => 3095248 [patent_doc_number] => 05318923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Method for forming a metal wiring layer in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/897294 [patent_app_country] => US [patent_app_date] => 1992-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1474 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/318/05318923.pdf [firstpage_image] =>[orig_patent_app_number] => 897294 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/897294
Method for forming a metal wiring layer in a semiconductor device Jun 10, 1992 Issued
Array ( [id] => 2960700 [patent_doc_number] => 05273931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Method of growing epitaxial layers of N-doped II-VI semiconductor compounds' [patent_app_type] => 1 [patent_app_number] => 7/894308 [patent_app_country] => US [patent_app_date] => 1992-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2707 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/273/05273931.pdf [firstpage_image] =>[orig_patent_app_number] => 894308 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/894308
Method of growing epitaxial layers of N-doped II-VI semiconductor compounds Jun 3, 1992 Issued
07/893075 INTEGRATED CIRCUIT WITH COMPLEMENTARY JUNCTION-ISOLATED BIPOLAR TRANSISTORS AND METHOD OF MAKING SAME May 31, 1992 Abandoned
Array ( [id] => 3061615 [patent_doc_number] => 05310692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Method of forming a MOSFET structure with planar surface' [patent_app_type] => 1 [patent_app_number] => 7/889822 [patent_app_country] => US [patent_app_date] => 1992-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2136 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/310/05310692.pdf [firstpage_image] =>[orig_patent_app_number] => 889822 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/889822
Method of forming a MOSFET structure with planar surface May 28, 1992 Issued
Array ( [id] => 2883933 [patent_doc_number] => 05268324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Modified silicon CMOS process having selectively deposited Si/SiGe FETS' [patent_app_type] => 1 [patent_app_number] => 7/890042 [patent_app_country] => US [patent_app_date] => 1992-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1881 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268324.pdf [firstpage_image] =>[orig_patent_app_number] => 890042 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/890042
Modified silicon CMOS process having selectively deposited Si/SiGe FETS May 26, 1992 Issued
Array ( [id] => 3426329 [patent_doc_number] => 05403729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Fabricating a semiconductor with an insulative coating' [patent_app_type] => 1 [patent_app_number] => 7/889832 [patent_app_country] => US [patent_app_date] => 1992-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 10680 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/403/05403729.pdf [firstpage_image] =>[orig_patent_app_number] => 889832 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/889832
Fabricating a semiconductor with an insulative coating May 26, 1992 Issued
Array ( [id] => 2953502 [patent_doc_number] => 05231055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-27 [patent_title] => 'Method of forming composite interconnect system' [patent_app_type] => 1 [patent_app_number] => 7/888777 [patent_app_country] => US [patent_app_date] => 1992-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3323 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/231/05231055.pdf [firstpage_image] =>[orig_patent_app_number] => 888777 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/888777
Method of forming composite interconnect system May 25, 1992 Issued
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