Hua Jasmine Song

Array ( [id] => 2974546 [patent_doc_number] => 05256564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Method for manufacturing semiconductor device having a contact structure' [patent_app_type] => 1 [patent_app_number] => 7/886938 [patent_app_country] => US [patent_app_date] => 1992-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2090 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/256/05256564.pdf [firstpage_image] =>[orig_patent_app_number] => 886938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2967506 [patent_doc_number] => 05258318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon' [patent_app_type] => 1 [patent_app_number] => 7/884510 [patent_app_country] => US [patent_app_date] => 1992-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2748 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258318.pdf [firstpage_image] =>[orig_patent_app_number] => 884510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3085989 [patent_doc_number] => 05278084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/880212 [patent_app_country] => US [patent_app_date] => 1992-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3214 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 533 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278084.pdf [firstpage_image] =>[orig_patent_app_number] => 880212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061578 [patent_doc_number] => 05310690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Method for forming integrated circuits having buried doped regions' [patent_app_type] => 1 [patent_app_number] => 7/880477 [patent_app_country] => US [patent_app_date] => 1992-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 4687 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/310/05310690.pdf [firstpage_image] =>[orig_patent_app_number] => 880477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2931629 [patent_doc_number] => 05196356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Method for manufacturing BICMOS devices' [patent_app_type] => 1 [patent_app_number] => 7/874612 [patent_app_country] => US [patent_app_date] => 1992-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 1687 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/196/05196356.pdf [firstpage_image] =>[orig_patent_app_number] => 874612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3038456 [patent_doc_number] => 05376561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'High density electronic circuit modules' [patent_app_type] => 1 [patent_app_number] => 7/874588 [patent_app_country] => US [patent_app_date] => 1992-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 67 [patent_no_of_words] => 10172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/376/05376561.pdf [firstpage_image] =>[orig_patent_app_number] => 874588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4021911 [patent_doc_number] => 05925574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method of producing a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/865646 [patent_app_country] => US [patent_app_date] => 1992-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4274 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925574.pdf [firstpage_image] =>[orig_patent_app_number] => 865646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3093098 [patent_doc_number] => 05292672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Method of manufacturing an insulated gate bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/862604 [patent_app_country] => US [patent_app_date] => 1992-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 10637 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/292/05292672.pdf [firstpage_image] =>[orig_patent_app_number] => 862604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2776098 [patent_doc_number] => 05151378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-29 [patent_title] => 'Self-aligned planar monolithic integrated circuit vertical transistor process' [patent_app_type] => 1 [patent_app_number] => 7/861404 [patent_app_country] => US [patent_app_date] => 1992-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 5245 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 838 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/151/05151378.pdf [firstpage_image] =>[orig_patent_app_number] => 861404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2782170 [patent_doc_number] => 05164326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Complementary bipolar and CMOS on SOI' [patent_app_type] => 1 [patent_app_number] => 7/860794 [patent_app_country] => US [patent_app_date] => 1992-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2697 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/164/05164326.pdf [firstpage_image] =>[orig_patent_app_number] => 860794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2985104 [patent_doc_number] => 05266504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-30 [patent_title] => 'Low temperature emitter process for high performance bipolar devices' [patent_app_type] => 1 [patent_app_number] => 7/857862 [patent_app_country] => US [patent_app_date] => 1992-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3485 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/266/05266504.pdf [firstpage_image] =>[orig_patent_app_number] => 857862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2958004 [patent_doc_number] => 05198375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Method for forming a bipolar transistor structure' [patent_app_type] => 1 [patent_app_number] => 7/856314 [patent_app_country] => US [patent_app_date] => 1992-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3689 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198375.pdf [firstpage_image] =>[orig_patent_app_number] => 856314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2961082 [patent_doc_number] => 05264378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Method for making a conductivity modulation MOSFET' [patent_app_type] => 1 [patent_app_number] => 7/853044 [patent_app_country] => US [patent_app_date] => 1992-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/264/05264378.pdf [firstpage_image] =>[orig_patent_app_number] => 853044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2948335 [patent_doc_number] => 05262338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Method for fabrication of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/850506 [patent_app_country] => US [patent_app_date] => 1992-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1293 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/262/05262338.pdf [firstpage_image] =>[orig_patent_app_number] => 850506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2985991 [patent_doc_number] => 05212104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-18 [patent_title] => 'Method for manufacturing an MOS transistor' [patent_app_type] => 1 [patent_app_number] => 7/848238 [patent_app_country] => US [patent_app_date] => 1992-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2159 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/212/05212104.pdf [firstpage_image] =>[orig_patent_app_number] => 848238 [rel_patent_id] =>[rel_patent_doc_number] =>)