Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3056805 [patent_doc_number] => 05338694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Method of fabricating BiCMOS device' [patent_app_type] => 1 [patent_app_number] => 7/847876 [patent_app_country] => US [patent_app_date] => 1992-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 6064 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 559 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338694.pdf [firstpage_image] =>[orig_patent_app_number] => 847876 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/847876
Method of fabricating BiCMOS device Mar 8, 1992 Issued
Array ( [id] => 2978864 [patent_doc_number] => 05204288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Method for planarizing an integrated circuit structure using low melting inorganic material' [patent_app_type] => 1 [patent_app_number] => 7/845544 [patent_app_country] => US [patent_app_date] => 1992-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5290 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204288.pdf [firstpage_image] =>[orig_patent_app_number] => 845544 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/845544
Method for planarizing an integrated circuit structure using low melting inorganic material Mar 3, 1992 Issued
Array ( [id] => 2988976 [patent_doc_number] => 05346834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Method for manufacturing a semiconductor device and a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/845063 [patent_app_country] => US [patent_app_date] => 1992-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 67 [patent_no_of_words] => 9680 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/346/05346834.pdf [firstpage_image] =>[orig_patent_app_number] => 845063 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/845063
Method for manufacturing a semiconductor device and a semiconductor memory device Mar 2, 1992 Issued
Array ( [id] => 2974051 [patent_doc_number] => 05208172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-04 [patent_title] => 'Method for forming a raised vertical transistor' [patent_app_type] => 1 [patent_app_number] => 7/844038 [patent_app_country] => US [patent_app_date] => 1992-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4796 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/208/05208172.pdf [firstpage_image] =>[orig_patent_app_number] => 844038 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/844038
Method for forming a raised vertical transistor Mar 1, 1992 Issued
Array ( [id] => 2976156 [patent_doc_number] => 05252500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/843346 [patent_app_country] => US [patent_app_date] => 1992-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3445 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/252/05252500.pdf [firstpage_image] =>[orig_patent_app_number] => 843346 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/843346
Method of fabricating a semiconductor device Feb 27, 1992 Issued
Array ( [id] => 2941817 [patent_doc_number] => 05254493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Method of fabricating integrated resistors in high density substrates' [patent_app_type] => 1 [patent_app_number] => 7/841311 [patent_app_country] => US [patent_app_date] => 1992-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 2845 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/254/05254493.pdf [firstpage_image] =>[orig_patent_app_number] => 841311 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/841311
Method of fabricating integrated resistors in high density substrates Feb 23, 1992 Issued
Array ( [id] => 2967488 [patent_doc_number] => 05258317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure' [patent_app_type] => 1 [patent_app_number] => 7/835200 [patent_app_country] => US [patent_app_date] => 1992-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1877 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258317.pdf [firstpage_image] =>[orig_patent_app_number] => 835200 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/835200
Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure Feb 12, 1992 Issued
Array ( [id] => 2909341 [patent_doc_number] => 05227318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method of making a cubic boron nitride bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/829834 [patent_app_country] => US [patent_app_date] => 1992-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5797 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227318.pdf [firstpage_image] =>[orig_patent_app_number] => 829834 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/829834
Method of making a cubic boron nitride bipolar transistor Feb 2, 1992 Issued
Array ( [id] => 2883729 [patent_doc_number] => 05268314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Method of forming a self-aligned bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/830783 [patent_app_country] => US [patent_app_date] => 1992-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3077 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268314.pdf [firstpage_image] =>[orig_patent_app_number] => 830783 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/830783
Method of forming a self-aligned bipolar transistor Feb 2, 1992 Issued
07/827138 EPITAXIAL SILICON STARTING MATERIAL Jan 27, 1992 Abandoned
Array ( [id] => 2799083 [patent_doc_number] => 05139959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Method for forming bipolar transistor input protection' [patent_app_type] => 1 [patent_app_number] => 7/822804 [patent_app_country] => US [patent_app_date] => 1992-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3348 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/139/05139959.pdf [firstpage_image] =>[orig_patent_app_number] => 822804 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/822804
Method for forming bipolar transistor input protection Jan 20, 1992 Issued
Array ( [id] => 2890132 [patent_doc_number] => 05270224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit' [patent_app_type] => 1 [patent_app_number] => 7/822232 [patent_app_country] => US [patent_app_date] => 1992-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6373 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270224.pdf [firstpage_image] =>[orig_patent_app_number] => 822232 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/822232
Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit Jan 16, 1992 Issued
Array ( [id] => 2883712 [patent_doc_number] => 05268313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Method of manufacturing a semiconductor device having a spacer' [patent_app_type] => 1 [patent_app_number] => 7/820454 [patent_app_country] => US [patent_app_date] => 1992-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 3561 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268313.pdf [firstpage_image] =>[orig_patent_app_number] => 820454 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/820454
Method of manufacturing a semiconductor device having a spacer Jan 12, 1992 Issued
Array ( [id] => 2893958 [patent_doc_number] => 05244822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Method of fabricating bipolar transistor using self-aligned polysilicon technology' [patent_app_type] => 1 [patent_app_number] => 7/818275 [patent_app_country] => US [patent_app_date] => 1992-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 44 [patent_no_of_words] => 8605 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/244/05244822.pdf [firstpage_image] =>[orig_patent_app_number] => 818275 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/818275
Method of fabricating bipolar transistor using self-aligned polysilicon technology Jan 7, 1992 Issued
Array ( [id] => 3073494 [patent_doc_number] => 05296389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Method of fabricating a heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/817860 [patent_app_country] => US [patent_app_date] => 1992-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4012 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296389.pdf [firstpage_image] =>[orig_patent_app_number] => 817860 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/817860
Method of fabricating a heterojunction bipolar transistor Jan 5, 1992 Issued
Array ( [id] => 2888328 [patent_doc_number] => 05244533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Method of manufacturing bipolar transistor operated at high speed' [patent_app_type] => 1 [patent_app_number] => 7/815786 [patent_app_country] => US [patent_app_date] => 1992-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 4252 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/244/05244533.pdf [firstpage_image] =>[orig_patent_app_number] => 815786 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/815786
Method of manufacturing bipolar transistor operated at high speed Jan 1, 1992 Issued
Array ( [id] => 2973766 [patent_doc_number] => 05225359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Method of fabricating Schottky barrier diodes and Schottky barrier diode-clamped transistors' [patent_app_type] => 1 [patent_app_number] => 7/812670 [patent_app_country] => US [patent_app_date] => 1991-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3926 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225359.pdf [firstpage_image] =>[orig_patent_app_number] => 812670 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/812670
Method of fabricating Schottky barrier diodes and Schottky barrier diode-clamped transistors Dec 22, 1991 Issued
07/812851 SEMICONDUCTOR DEVICE HAVING WIRING ELECTRODES Dec 19, 1991 Abandoned
Array ( [id] => 2933538 [patent_doc_number] => 05246871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Method of manufacturing a semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip' [patent_app_type] => 1 [patent_app_number] => 7/805048 [patent_app_country] => US [patent_app_date] => 1991-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2146 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/246/05246871.pdf [firstpage_image] =>[orig_patent_app_number] => 805048 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/805048
Method of manufacturing a semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip Dec 10, 1991 Issued
Array ( [id] => 2894324 [patent_doc_number] => 05244841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing' [patent_app_type] => 1 [patent_app_number] => 7/805423 [patent_app_country] => US [patent_app_date] => 1991-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4493 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/244/05244841.pdf [firstpage_image] =>[orig_patent_app_number] => 805423 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/805423
Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing Dec 9, 1991 Issued
Menu