Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2952191 [patent_doc_number] => 05198071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Process for inhibiting slip and microcracking while forming epitaxial layer on semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 7/797614 [patent_app_country] => US [patent_app_date] => 1991-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4980 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198071.pdf [firstpage_image] =>[orig_patent_app_number] => 797614 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/797614
Process for inhibiting slip and microcracking while forming epitaxial layer on semiconductor wafer Nov 24, 1991 Issued
07/794922 DEVICE RELIABILITY OF MOS DEVICES USING SILICON RICH PLASMA OXIDE FILMS Nov 19, 1991 Abandoned
Array ( [id] => 3059777 [patent_doc_number] => 05294295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges' [patent_app_type] => 1 [patent_app_number] => 7/786322 [patent_app_country] => US [patent_app_date] => 1991-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1362 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/294/05294295.pdf [firstpage_image] =>[orig_patent_app_number] => 786322 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/786322
Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges Oct 30, 1991 Issued
Array ( [id] => 2934954 [patent_doc_number] => 05254137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Method of producing chip-type solid-electrolyte capacitor' [patent_app_type] => 1 [patent_app_number] => 7/783982 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2323 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/254/05254137.pdf [firstpage_image] =>[orig_patent_app_number] => 783982 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/783982
Method of producing chip-type solid-electrolyte capacitor Oct 28, 1991 Issued
Array ( [id] => 2804415 [patent_doc_number] => 05147813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Erase performance improvement via dual floating gate processing' [patent_app_type] => 1 [patent_app_number] => 7/784134 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4226 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/147/05147813.pdf [firstpage_image] =>[orig_patent_app_number] => 784134 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/784134
Erase performance improvement via dual floating gate processing Oct 28, 1991 Issued
Array ( [id] => 2933687 [patent_doc_number] => 05246879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Method of forming nanometer-scale trenches and holes' [patent_app_type] => 1 [patent_app_number] => 7/782197 [patent_app_country] => US [patent_app_date] => 1991-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3254 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/246/05246879.pdf [firstpage_image] =>[orig_patent_app_number] => 782197 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/782197
Method of forming nanometer-scale trenches and holes Oct 23, 1991 Issued
Array ( [id] => 2929573 [patent_doc_number] => 05232876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'Method for manufacturing a silicon layer having increased surface area' [patent_app_type] => 1 [patent_app_number] => 7/781992 [patent_app_country] => US [patent_app_date] => 1991-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3384 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/232/05232876.pdf [firstpage_image] =>[orig_patent_app_number] => 781992 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/781992
Method for manufacturing a silicon layer having increased surface area Oct 22, 1991 Issued
Array ( [id] => 2946228 [patent_doc_number] => 05180681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-19 [patent_title] => 'Method of making high current, high voltage breakdown field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/781096 [patent_app_country] => US [patent_app_date] => 1991-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/180/05180681.pdf [firstpage_image] =>[orig_patent_app_number] => 781096 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/781096
Method of making high current, high voltage breakdown field effect transistor Oct 21, 1991 Issued
07/774123 SEMICONDUCTOR DEVICE HAVING A BOROSILICATE GLASS SPACER AND METHOD OF FABRICATION Oct 9, 1991 Abandoned
Array ( [id] => 2884134 [patent_doc_number] => 05268333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Method of reflowing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/772870 [patent_app_country] => US [patent_app_date] => 1991-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 1313 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268333.pdf [firstpage_image] =>[orig_patent_app_number] => 772870 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/772870
Method of reflowing a semiconductor device Oct 7, 1991 Issued
Array ( [id] => 2931687 [patent_doc_number] => 05196359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Method of forming heterostructure field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/710596 [patent_app_country] => US [patent_app_date] => 1991-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3298 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/196/05196359.pdf [firstpage_image] =>[orig_patent_app_number] => 710596 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/710596
Method of forming heterostructure field effect transistor Oct 4, 1991 Issued
90/002464 METHOD FOR MAKING TRANSISTOR STRUCTURES Sep 30, 1991 Issued
07/765758 METHOD OF MANUFACTURING MASK ALIGNMENT MARKS Sep 25, 1991 Abandoned
Array ( [id] => 2887399 [patent_doc_number] => 05238865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Process for producing laminated semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 7/763302 [patent_app_country] => US [patent_app_date] => 1991-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 2684 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/238/05238865.pdf [firstpage_image] =>[orig_patent_app_number] => 763302 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/763302
Process for producing laminated semiconductor substrate Sep 19, 1991 Issued
Array ( [id] => 2941083 [patent_doc_number] => 05223454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'Method of manufacturing semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/760889 [patent_app_country] => US [patent_app_date] => 1991-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 13374 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/223/05223454.pdf [firstpage_image] =>[orig_patent_app_number] => 760889 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/760889
Method of manufacturing semiconductor integrated circuit device Sep 16, 1991 Issued
07/755340 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME Sep 4, 1991 Abandoned
Array ( [id] => 2978572 [patent_doc_number] => 05204274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/750856 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 42 [patent_no_of_words] => 11640 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 515 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204274.pdf [firstpage_image] =>[orig_patent_app_number] => 750856 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/750856
Method of fabricating semiconductor device Aug 28, 1991 Issued
Array ( [id] => 2857545 [patent_doc_number] => 05149672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-22 [patent_title] => 'Process for fabricating integrated circuits having shallow junctions' [patent_app_type] => 1 [patent_app_number] => 7/754361 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3125 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/149/05149672.pdf [firstpage_image] =>[orig_patent_app_number] => 754361 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/754361
Process for fabricating integrated circuits having shallow junctions Aug 28, 1991 Issued
Array ( [id] => 2973748 [patent_doc_number] => 05225358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Method of forming late isolation with polishing' [patent_app_type] => 1 [patent_app_number] => 7/749257 [patent_app_country] => US [patent_app_date] => 1991-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2211 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225358.pdf [firstpage_image] =>[orig_patent_app_number] => 749257 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/749257
Method of forming late isolation with polishing Aug 22, 1991 Issued
Array ( [id] => 2929937 [patent_doc_number] => 05219767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Process for preparing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/748694 [patent_app_country] => US [patent_app_date] => 1991-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 2093 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/219/05219767.pdf [firstpage_image] =>[orig_patent_app_number] => 748694 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/748694
Process for preparing semiconductor device Aug 21, 1991 Issued
Menu