| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2952191
[patent_doc_number] => 05198071
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-30
[patent_title] => 'Process for inhibiting slip and microcracking while forming epitaxial layer on semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 7/797614
[patent_app_country] => US
[patent_app_date] => 1991-11-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/198/05198071.pdf
[firstpage_image] =>[orig_patent_app_number] => 797614
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/797614 | Process for inhibiting slip and microcracking while forming epitaxial layer on semiconductor wafer | Nov 24, 1991 | Issued |
| 07/794922 | DEVICE RELIABILITY OF MOS DEVICES USING SILICON RICH PLASMA OXIDE FILMS | Nov 19, 1991 | Abandoned |
Array
(
[id] => 3059777
[patent_doc_number] => 05294295
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-15
[patent_title] => 'Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges'
[patent_app_type] => 1
[patent_app_number] => 7/786322
[patent_app_country] => US
[patent_app_date] => 1991-10-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/294/05294295.pdf
[firstpage_image] =>[orig_patent_app_number] => 786322
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/786322 | Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges | Oct 30, 1991 | Issued |
Array
(
[id] => 2934954
[patent_doc_number] => 05254137
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-19
[patent_title] => 'Method of producing chip-type solid-electrolyte capacitor'
[patent_app_type] => 1
[patent_app_number] => 7/783982
[patent_app_country] => US
[patent_app_date] => 1991-10-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/254/05254137.pdf
[firstpage_image] =>[orig_patent_app_number] => 783982
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/783982 | Method of producing chip-type solid-electrolyte capacitor | Oct 28, 1991 | Issued |
Array
(
[id] => 2804415
[patent_doc_number] => 05147813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-15
[patent_title] => 'Erase performance improvement via dual floating gate processing'
[patent_app_type] => 1
[patent_app_number] => 7/784134
[patent_app_country] => US
[patent_app_date] => 1991-10-29
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/147/05147813.pdf
[firstpage_image] =>[orig_patent_app_number] => 784134
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/784134 | Erase performance improvement via dual floating gate processing | Oct 28, 1991 | Issued |
Array
(
[id] => 2933687
[patent_doc_number] => 05246879
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-21
[patent_title] => 'Method of forming nanometer-scale trenches and holes'
[patent_app_type] => 1
[patent_app_number] => 7/782197
[patent_app_country] => US
[patent_app_date] => 1991-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/246/05246879.pdf
[firstpage_image] =>[orig_patent_app_number] => 782197
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/782197 | Method of forming nanometer-scale trenches and holes | Oct 23, 1991 | Issued |
Array
(
[id] => 2929573
[patent_doc_number] => 05232876
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-03
[patent_title] => 'Method for manufacturing a silicon layer having increased surface area'
[patent_app_type] => 1
[patent_app_number] => 7/781992
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[patent_app_date] => 1991-10-23
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[pdf_file] => patents/05/232/05232876.pdf
[firstpage_image] =>[orig_patent_app_number] => 781992
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/781992 | Method for manufacturing a silicon layer having increased surface area | Oct 22, 1991 | Issued |
Array
(
[id] => 2946228
[patent_doc_number] => 05180681
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-19
[patent_title] => 'Method of making high current, high voltage breakdown field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 7/781096
[patent_app_country] => US
[patent_app_date] => 1991-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/180/05180681.pdf
[firstpage_image] =>[orig_patent_app_number] => 781096
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/781096 | Method of making high current, high voltage breakdown field effect transistor | Oct 21, 1991 | Issued |
| 07/774123 | SEMICONDUCTOR DEVICE HAVING A BOROSILICATE GLASS SPACER AND METHOD OF FABRICATION | Oct 9, 1991 | Abandoned |
Array
(
[id] => 2884134
[patent_doc_number] => 05268333
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-07
[patent_title] => 'Method of reflowing a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/772870
[patent_app_country] => US
[patent_app_date] => 1991-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/268/05268333.pdf
[firstpage_image] =>[orig_patent_app_number] => 772870
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/772870 | Method of reflowing a semiconductor device | Oct 7, 1991 | Issued |
Array
(
[id] => 2931687
[patent_doc_number] => 05196359
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-23
[patent_title] => 'Method of forming heterostructure field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 7/710596
[patent_app_country] => US
[patent_app_date] => 1991-10-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/196/05196359.pdf
[firstpage_image] =>[orig_patent_app_number] => 710596
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/710596 | Method of forming heterostructure field effect transistor | Oct 4, 1991 | Issued |
| 90/002464 | METHOD FOR MAKING TRANSISTOR STRUCTURES | Sep 30, 1991 | Issued |
| 07/765758 | METHOD OF MANUFACTURING MASK ALIGNMENT MARKS | Sep 25, 1991 | Abandoned |
Array
(
[id] => 2887399
[patent_doc_number] => 05238865
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-24
[patent_title] => 'Process for producing laminated semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 7/763302
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[patent_app_date] => 1991-09-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/238/05238865.pdf
[firstpage_image] =>[orig_patent_app_number] => 763302
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/763302 | Process for producing laminated semiconductor substrate | Sep 19, 1991 | Issued |
Array
(
[id] => 2941083
[patent_doc_number] => 05223454
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-29
[patent_title] => 'Method of manufacturing semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 7/760889
[patent_app_country] => US
[patent_app_date] => 1991-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => patents/05/223/05223454.pdf
[firstpage_image] =>[orig_patent_app_number] => 760889
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/760889 | Method of manufacturing semiconductor integrated circuit device | Sep 16, 1991 | Issued |
| 07/755340 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME | Sep 4, 1991 | Abandoned |
Array
(
[id] => 2978572
[patent_doc_number] => 05204274
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[patent_kind] => NA
[patent_issue_date] => 1993-04-20
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[firstpage_image] =>[orig_patent_app_number] => 750856
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/750856 | Method of fabricating semiconductor device | Aug 28, 1991 | Issued |
Array
(
[id] => 2857545
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[patent_issue_date] => 1992-09-22
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[firstpage_image] =>[orig_patent_app_number] => 754361
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/754361 | Process for fabricating integrated circuits having shallow junctions | Aug 28, 1991 | Issued |
Array
(
[id] => 2973748
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[patent_kind] => NA
[patent_issue_date] => 1993-07-06
[patent_title] => 'Method of forming late isolation with polishing'
[patent_app_type] => 1
[patent_app_number] => 7/749257
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[pdf_file] => patents/05/225/05225358.pdf
[firstpage_image] =>[orig_patent_app_number] => 749257
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/749257 | Method of forming late isolation with polishing | Aug 22, 1991 | Issued |
Array
(
[id] => 2929937
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[patent_issue_date] => 1993-06-15
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[firstpage_image] =>[orig_patent_app_number] => 748694
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/748694 | Process for preparing semiconductor device | Aug 21, 1991 | Issued |