Hua Jasmine Song

Array ( [id] => 2903271 [patent_doc_number] => 05248625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Techniques for forming isolation structures' [patent_app_type] => 1 [patent_app_number] => 7/748853 [patent_app_country] => US [patent_app_date] => 1991-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4963 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/248/05248625.pdf [firstpage_image] =>[orig_patent_app_number] => 748853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2804340 [patent_doc_number] => 05147809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Method of producing a bipolar transistor with a laterally graded emitter (LGE) employing a refill method of polycrystalline silicon' [patent_app_type] => 1 [patent_app_number] => 7/747634 [patent_app_country] => US [patent_app_date] => 1991-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2259 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/147/05147809.pdf [firstpage_image] =>[orig_patent_app_number] => 747634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2931347 [patent_doc_number] => 05188974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-23 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/747486 [patent_app_country] => US [patent_app_date] => 1991-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 2995 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/188/05188974.pdf [firstpage_image] =>[orig_patent_app_number] => 747486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2909302 [patent_doc_number] => 05227316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size' [patent_app_type] => 1 [patent_app_number] => 7/744191 [patent_app_country] => US [patent_app_date] => 1991-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 7664 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227316.pdf [firstpage_image] =>[orig_patent_app_number] => 744191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2883949 [patent_doc_number] => 05268325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Method for fabricating a polycrystalline silicon resistive load element in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/741793 [patent_app_country] => US [patent_app_date] => 1991-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2138 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268325.pdf [firstpage_image] =>[orig_patent_app_number] => 741793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2931964 [patent_doc_number] => 05196375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Method for manufacturing bonded semiconductor body' [patent_app_type] => 1 [patent_app_number] => 7/737805 [patent_app_country] => US [patent_app_date] => 1991-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3346 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/196/05196375.pdf [firstpage_image] =>[orig_patent_app_number] => 737805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2772304 [patent_doc_number] => 05132234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Method of producing a bipolar CMOS device' [patent_app_type] => 1 [patent_app_number] => 7/727532 [patent_app_country] => US [patent_app_date] => 1991-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 1805 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132234.pdf [firstpage_image] =>[orig_patent_app_number] => 727532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2898895 [patent_doc_number] => 05217912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/723217 [patent_app_country] => US [patent_app_date] => 1991-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3447 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/217/05217912.pdf [firstpage_image] =>[orig_patent_app_number] => 723217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2973985 [patent_doc_number] => 05208169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-04 [patent_title] => 'Method of forming high voltage bipolar transistor for a BICMOS integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/724574 [patent_app_country] => US [patent_app_date] => 1991-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3403 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/208/05208169.pdf [firstpage_image] =>[orig_patent_app_number] => 724574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2839100 [patent_doc_number] => 05171697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-15 [patent_title] => 'Method of forming multiple layer collector structure for bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/722984 [patent_app_country] => US [patent_app_date] => 1991-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3815 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/171/05171697.pdf [firstpage_image] =>[orig_patent_app_number] => 722984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2890695 [patent_doc_number] => 05270253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Method of producing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/719109 [patent_app_country] => US [patent_app_date] => 1991-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2300 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270253.pdf [firstpage_image] =>[orig_patent_app_number] => 719109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2828481 [patent_doc_number] => 05128272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Self-aligned planar monolithic integrated circuit vertical transistor process' [patent_app_type] => 1 [patent_app_number] => 7/716890 [patent_app_country] => US [patent_app_date] => 1991-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 5244 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/128/05128272.pdf [firstpage_image] =>[orig_patent_app_number] => 716890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2893940 [patent_doc_number] => 05244821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Bipolar fabrication method' [patent_app_type] => 1 [patent_app_number] => 7/712316 [patent_app_country] => US [patent_app_date] => 1991-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1121 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/244/05244821.pdf [firstpage_image] =>[orig_patent_app_number] => 712316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2866369 [patent_doc_number] => 05153146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-06 [patent_title] => 'Maufacturing method of semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/705570 [patent_app_country] => US [patent_app_date] => 1991-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3038 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/153/05153146.pdf [firstpage_image] =>[orig_patent_app_number] => 705570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2784255 [patent_doc_number] => 05130262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-14 [patent_title] => 'Internal current limit and overvoltage protection method' [patent_app_type] => 1 [patent_app_number] => 7/704683 [patent_app_country] => US [patent_app_date] => 1991-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2362 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/130/05130262.pdf [firstpage_image] =>[orig_patent_app_number] => 704683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2799099 [patent_doc_number] => 05139960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Interstitital doping in III-V semiconductors to avoid or suppress DX center formation' [patent_app_type] => 1 [patent_app_number] => 7/700101 [patent_app_country] => US [patent_app_date] => 1991-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 12396 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/139/05139960.pdf [firstpage_image] =>[orig_patent_app_number] => 700101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2940995 [patent_doc_number] => 05223449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'Method of making an integrated circuit composed of group III-V compound field effect and bipolar semiconductors' [patent_app_type] => 1 [patent_app_number] => 7/692326 [patent_app_country] => US [patent_app_date] => 1991-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 68 [patent_no_of_words] => 13079 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/223/05223449.pdf [firstpage_image] =>[orig_patent_app_number] => 692326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2772445 [patent_doc_number] => 05132241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Method of manufacturing minimum counterdoping in twin well process' [patent_app_type] => 1 [patent_app_number] => 7/684830 [patent_app_country] => US [patent_app_date] => 1991-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132241.pdf [firstpage_image] =>[orig_patent_app_number] => 684830 [rel_patent_id] =>[rel_patent_doc_number] =>)