Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2789350 [patent_doc_number] => 05102810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-07 [patent_title] => 'Method for controlling the switching speed of bipolar power devices' [patent_app_type] => 1 [patent_app_number] => 7/684682 [patent_app_country] => US [patent_app_date] => 1991-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3248 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/102/05102810.pdf [firstpage_image] =>[orig_patent_app_number] => 684682 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/684682
Method for controlling the switching speed of bipolar power devices Apr 10, 1991 Issued
Array ( [id] => 2844898 [patent_doc_number] => 05106767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'Process for fabricating low capacitance bipolar junction transistor' [patent_app_type] => 1 [patent_app_number] => 7/683408 [patent_app_country] => US [patent_app_date] => 1991-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6603 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/106/05106767.pdf [firstpage_image] =>[orig_patent_app_number] => 683408 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/683408
Process for fabricating low capacitance bipolar junction transistor Apr 9, 1991 Issued
Array ( [id] => 2957952 [patent_doc_number] => 05198372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Method for making a shallow junction bipolar transistor and transistor formed thereby' [patent_app_type] => 1 [patent_app_number] => 7/679896 [patent_app_country] => US [patent_app_date] => 1991-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3015 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198372.pdf [firstpage_image] =>[orig_patent_app_number] => 679896 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/679896
Method for making a shallow junction bipolar transistor and transistor formed thereby Apr 2, 1991 Issued
Array ( [id] => 2829601 [patent_doc_number] => 05175125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Method for making electrical contacts' [patent_app_type] => 1 [patent_app_number] => 7/680156 [patent_app_country] => US [patent_app_date] => 1991-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2915 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175125.pdf [firstpage_image] =>[orig_patent_app_number] => 680156 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/680156
Method for making electrical contacts Apr 2, 1991 Issued
Array ( [id] => 2772322 [patent_doc_number] => 05132235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Method for fabricating a high voltage MOS transistor' [patent_app_type] => 1 [patent_app_number] => 7/678578 [patent_app_country] => US [patent_app_date] => 1991-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2919 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132235.pdf [firstpage_image] =>[orig_patent_app_number] => 678578 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/678578
Method for fabricating a high voltage MOS transistor Mar 28, 1991 Issued
Array ( [id] => 2925695 [patent_doc_number] => 05228927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Method for heat-treating gallium arsenide monocrystals' [patent_app_type] => 1 [patent_app_number] => 7/677036 [patent_app_country] => US [patent_app_date] => 1991-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4476 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/228/05228927.pdf [firstpage_image] =>[orig_patent_app_number] => 677036 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/677036
Method for heat-treating gallium arsenide monocrystals Mar 28, 1991 Issued
Array ( [id] => 2877570 [patent_doc_number] => 05185279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Method of manufacturing insulated-gate type field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/673669 [patent_app_country] => US [patent_app_date] => 1991-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 24 [patent_no_of_words] => 3366 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185279.pdf [firstpage_image] =>[orig_patent_app_number] => 673669 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/673669
Method of manufacturing insulated-gate type field effect transistor Mar 21, 1991 Issued
Array ( [id] => 2829486 [patent_doc_number] => 05175119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Method of producing insulated-gate field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/670806 [patent_app_country] => US [patent_app_date] => 1991-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5223 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175119.pdf [firstpage_image] =>[orig_patent_app_number] => 670806 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/670806
Method of producing insulated-gate field effect transistor Mar 17, 1991 Issued
Array ( [id] => 2734662 [patent_doc_number] => 05077231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Method to integrate HBTs and FETs' [patent_app_type] => 1 [patent_app_number] => 7/670094 [patent_app_country] => US [patent_app_date] => 1991-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2819 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077231.pdf [firstpage_image] =>[orig_patent_app_number] => 670094 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/670094
Method to integrate HBTs and FETs Mar 14, 1991 Issued
Array ( [id] => 2784570 [patent_doc_number] => 05093275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-03 [patent_title] => 'Method for forming hot-carrier suppressed sub-micron MISFET device' [patent_app_type] => 1 [patent_app_number] => 7/655674 [patent_app_country] => US [patent_app_date] => 1991-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3661 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/093/05093275.pdf [firstpage_image] =>[orig_patent_app_number] => 655674 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/655674
Method for forming hot-carrier suppressed sub-micron MISFET device Feb 13, 1991 Issued
Array ( [id] => 2799136 [patent_doc_number] => 05139962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'MOS fabrication method with self-aligned gate' [patent_app_type] => 1 [patent_app_number] => 7/653312 [patent_app_country] => US [patent_app_date] => 1991-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1872 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/139/05139962.pdf [firstpage_image] =>[orig_patent_app_number] => 653312 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/653312
MOS fabrication method with self-aligned gate Feb 10, 1991 Issued
Array ( [id] => 2668288 [patent_doc_number] => 05070029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-03 [patent_title] => 'Semiconductor process using selective deposition' [patent_app_type] => 1 [patent_app_number] => 7/650324 [patent_app_country] => US [patent_app_date] => 1991-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3596 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/070/05070029.pdf [firstpage_image] =>[orig_patent_app_number] => 650324 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/650324
Semiconductor process using selective deposition Feb 3, 1991 Issued
Array ( [id] => 2787498 [patent_doc_number] => 05100831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/649640 [patent_app_country] => US [patent_app_date] => 1991-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 5353 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/100/05100831.pdf [firstpage_image] =>[orig_patent_app_number] => 649640 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/649640
Method for fabricating semiconductor device Jan 31, 1991 Issued
Array ( [id] => 2834331 [patent_doc_number] => 05120673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Process of fabricating field effect transistor with LDD structure' [patent_app_type] => 1 [patent_app_number] => 7/645770 [patent_app_country] => US [patent_app_date] => 1991-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3171 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/120/05120673.pdf [firstpage_image] =>[orig_patent_app_number] => 645770 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/645770
Process of fabricating field effect transistor with LDD structure Jan 24, 1991 Issued
Array ( [id] => 2978626 [patent_doc_number] => 05204276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/645313 [patent_app_country] => US [patent_app_date] => 1991-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 8258 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 432 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204276.pdf [firstpage_image] =>[orig_patent_app_number] => 645313 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/645313
Method of manufacturing semiconductor device Jan 23, 1991 Issued
07/644415 METHOD FOR PLANARIZATION AN INTEGRATED CIRCUIT STRUCTURE USING LOW MELTING INORGANIC MATERIAL Jan 21, 1991 Abandoned
Array ( [id] => 2853518 [patent_doc_number] => 05112776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing' [patent_app_type] => 1 [patent_app_number] => 7/644853 [patent_app_country] => US [patent_app_date] => 1991-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4480 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/112/05112776.pdf [firstpage_image] =>[orig_patent_app_number] => 644853 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/644853
Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing Jan 21, 1991 Issued
Array ( [id] => 2800665 [patent_doc_number] => 05124271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Process for fabricating a BiCMOS integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/642611 [patent_app_country] => US [patent_app_date] => 1991-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6983 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124271.pdf [firstpage_image] =>[orig_patent_app_number] => 642611 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/642611
Process for fabricating a BiCMOS integrated circuit Jan 16, 1991 Issued
Array ( [id] => 2804358 [patent_doc_number] => 05147810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Process for producing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/639064 [patent_app_country] => US [patent_app_date] => 1991-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 11408 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/147/05147810.pdf [firstpage_image] =>[orig_patent_app_number] => 639064 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/639064
Process for producing semiconductor device Jan 8, 1991 Issued
Array ( [id] => 2707236 [patent_doc_number] => 05041394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-20 [patent_title] => 'Method for forming protective barrier on silicided regions' [patent_app_type] => 1 [patent_app_number] => 7/634970 [patent_app_country] => US [patent_app_date] => 1991-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1315 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/041/05041394.pdf [firstpage_image] =>[orig_patent_app_number] => 634970 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/634970
Method for forming protective barrier on silicided regions Jan 6, 1991 Issued
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