
Hua Jasmine Song
Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )
| Most Active Art Unit | 2133 |
| Art Unit(s) | 2131, 2189, 2187, 2138, 2133, 2188 |
| Total Applications | 1393 |
| Issued Applications | 1256 |
| Pending Applications | 72 |
| Abandoned Applications | 80 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2789350
[patent_doc_number] => 05102810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-07
[patent_title] => 'Method for controlling the switching speed of bipolar power devices'
[patent_app_type] => 1
[patent_app_number] => 7/684682
[patent_app_country] => US
[patent_app_date] => 1991-04-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/102/05102810.pdf
[firstpage_image] =>[orig_patent_app_number] => 684682
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/684682 | Method for controlling the switching speed of bipolar power devices | Apr 10, 1991 | Issued |
Array
(
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[patent_doc_number] => 05106767
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[patent_kind] => NA
[patent_issue_date] => 1992-04-21
[patent_title] => 'Process for fabricating low capacitance bipolar junction transistor'
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[patent_app_number] => 7/683408
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/683408 | Process for fabricating low capacitance bipolar junction transistor | Apr 9, 1991 | Issued |
Array
(
[id] => 2957952
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[patent_kind] => NA
[patent_issue_date] => 1993-03-30
[patent_title] => 'Method for making a shallow junction bipolar transistor and transistor formed thereby'
[patent_app_type] => 1
[patent_app_number] => 7/679896
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[patent_app_date] => 1991-04-03
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[firstpage_image] =>[orig_patent_app_number] => 679896
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/679896 | Method for making a shallow junction bipolar transistor and transistor formed thereby | Apr 2, 1991 | Issued |
Array
(
[id] => 2829601
[patent_doc_number] => 05175125
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-29
[patent_title] => 'Method for making electrical contacts'
[patent_app_type] => 1
[patent_app_number] => 7/680156
[patent_app_country] => US
[patent_app_date] => 1991-04-03
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[firstpage_image] =>[orig_patent_app_number] => 680156
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/680156 | Method for making electrical contacts | Apr 2, 1991 | Issued |
Array
(
[id] => 2772322
[patent_doc_number] => 05132235
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[patent_kind] => NA
[patent_issue_date] => 1992-07-21
[patent_title] => 'Method for fabricating a high voltage MOS transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/678578 | Method for fabricating a high voltage MOS transistor | Mar 28, 1991 | Issued |
Array
(
[id] => 2925695
[patent_doc_number] => 05228927
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-20
[patent_title] => 'Method for heat-treating gallium arsenide monocrystals'
[patent_app_type] => 1
[patent_app_number] => 7/677036
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[firstpage_image] =>[orig_patent_app_number] => 677036
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/677036 | Method for heat-treating gallium arsenide monocrystals | Mar 28, 1991 | Issued |
Array
(
[id] => 2877570
[patent_doc_number] => 05185279
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[patent_kind] => NA
[patent_issue_date] => 1993-02-09
[patent_title] => 'Method of manufacturing insulated-gate type field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 7/673669
[patent_app_country] => US
[patent_app_date] => 1991-03-22
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[pdf_file] => patents/05/185/05185279.pdf
[firstpage_image] =>[orig_patent_app_number] => 673669
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/673669 | Method of manufacturing insulated-gate type field effect transistor | Mar 21, 1991 | Issued |
Array
(
[id] => 2829486
[patent_doc_number] => 05175119
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-29
[patent_title] => 'Method of producing insulated-gate field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 7/670806
[patent_app_country] => US
[patent_app_date] => 1991-03-18
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[patent_drawing_sheets_cnt] => 12
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[pdf_file] => patents/05/175/05175119.pdf
[firstpage_image] =>[orig_patent_app_number] => 670806
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/670806 | Method of producing insulated-gate field effect transistor | Mar 17, 1991 | Issued |
Array
(
[id] => 2734662
[patent_doc_number] => 05077231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Method to integrate HBTs and FETs'
[patent_app_type] => 1
[patent_app_number] => 7/670094
[patent_app_country] => US
[patent_app_date] => 1991-03-15
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[pdf_file] => patents/05/077/05077231.pdf
[firstpage_image] =>[orig_patent_app_number] => 670094
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/670094 | Method to integrate HBTs and FETs | Mar 14, 1991 | Issued |
Array
(
[id] => 2784570
[patent_doc_number] => 05093275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-03
[patent_title] => 'Method for forming hot-carrier suppressed sub-micron MISFET device'
[patent_app_type] => 1
[patent_app_number] => 7/655674
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[patent_app_date] => 1991-02-14
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[pdf_file] => patents/05/093/05093275.pdf
[firstpage_image] =>[orig_patent_app_number] => 655674
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/655674 | Method for forming hot-carrier suppressed sub-micron MISFET device | Feb 13, 1991 | Issued |
Array
(
[id] => 2799136
[patent_doc_number] => 05139962
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-18
[patent_title] => 'MOS fabrication method with self-aligned gate'
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[pdf_file] => patents/05/139/05139962.pdf
[firstpage_image] =>[orig_patent_app_number] => 653312
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/653312 | MOS fabrication method with self-aligned gate | Feb 10, 1991 | Issued |
Array
(
[id] => 2668288
[patent_doc_number] => 05070029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-03
[patent_title] => 'Semiconductor process using selective deposition'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/650324 | Semiconductor process using selective deposition | Feb 3, 1991 | Issued |
Array
(
[id] => 2787498
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[firstpage_image] =>[orig_patent_app_number] => 649640
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/649640 | Method for fabricating semiconductor device | Jan 31, 1991 | Issued |
Array
(
[id] => 2834331
[patent_doc_number] => 05120673
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[patent_issue_date] => 1992-06-09
[patent_title] => 'Process of fabricating field effect transistor with LDD structure'
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[pdf_file] => patents/05/120/05120673.pdf
[firstpage_image] =>[orig_patent_app_number] => 645770
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/645770 | Process of fabricating field effect transistor with LDD structure | Jan 24, 1991 | Issued |
Array
(
[id] => 2978626
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[firstpage_image] =>[orig_patent_app_number] => 645313
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/645313 | Method of manufacturing semiconductor device | Jan 23, 1991 | Issued |
| 07/644415 | METHOD FOR PLANARIZATION AN INTEGRATED CIRCUIT STRUCTURE USING LOW MELTING INORGANIC MATERIAL | Jan 21, 1991 | Abandoned |
Array
(
[id] => 2853518
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[patent_title] => 'Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing'
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Array
(
[id] => 2800665
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Array
(
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Array
(
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