| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2866072
[patent_doc_number] => 05162260
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-10
[patent_title] => 'Stacked solid via formation in integrated circuit systems'
[patent_app_type] => 1
[patent_app_number] => 7/638885
[patent_app_country] => US
[patent_app_date] => 1991-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 4423
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/162/05162260.pdf
[firstpage_image] =>[orig_patent_app_number] => 638885
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/638885 | Stacked solid via formation in integrated circuit systems | Jan 6, 1991 | Issued |
| 07/637240 | METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING A CMOS STRUCTURE HAVING DOUBLE-DOPED CHANNEL REGIONS | Jan 2, 1991 | Abandoned |
Array
(
[id] => 2871446
[patent_doc_number] => 05091340
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-25
[patent_title] => 'Method for forming multilayer wirings on a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/635810
[patent_app_country] => US
[patent_app_date] => 1991-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1613
[patent_no_of_claims] => 6
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[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/091/05091340.pdf
[firstpage_image] =>[orig_patent_app_number] => 635810
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/635810 | Method for forming multilayer wirings on a semiconductor device | Jan 1, 1991 | Issued |
Array
(
[id] => 2931292
[patent_doc_number] => 05188971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-23
[patent_title] => 'Process for making a self-aligned bipolar sinker structure'
[patent_app_type] => 1
[patent_app_number] => 7/635684
[patent_app_country] => US
[patent_app_date] => 1990-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2478
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/188/05188971.pdf
[firstpage_image] =>[orig_patent_app_number] => 635684
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/635684 | Process for making a self-aligned bipolar sinker structure | Dec 26, 1990 | Issued |
Array
(
[id] => 2978608
[patent_doc_number] => 05204275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-20
[patent_title] => 'Method for fabricating compact bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 7/633906
[patent_app_country] => US
[patent_app_date] => 1990-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2061
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/204/05204275.pdf
[firstpage_image] =>[orig_patent_app_number] => 633906
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/633906 | Method for fabricating compact bipolar transistor | Dec 25, 1990 | Issued |
| 07/632437 | IMPROVED METHOD FOR FORMING INTEGRATED CIRCUITS HAVING BURIED DOPED REGIONS | Dec 20, 1990 | Abandoned |
Array
(
[id] => 2709203
[patent_doc_number] => 05061646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-29
[patent_title] => 'Method for forming a self-aligned bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 7/631174
[patent_app_country] => US
[patent_app_date] => 1990-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4915
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/061/05061646.pdf
[firstpage_image] =>[orig_patent_app_number] => 631174
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/631174 | Method for forming a self-aligned bipolar transistor | Dec 18, 1990 | Issued |
Array
(
[id] => 2857068
[patent_doc_number] => 05084401
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-28
[patent_title] => 'Insulated gate bipolar transistor and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 7/627870
[patent_app_country] => US
[patent_app_date] => 1990-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5252
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/084/05084401.pdf
[firstpage_image] =>[orig_patent_app_number] => 627870
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/627870 | Insulated gate bipolar transistor and method of manufacturing the same | Dec 16, 1990 | Issued |
| 07/627160 | FABRICATION PROCESS FOR SCHOTTKY BARRIER DIODES ON A SINGLE POLY BIPOLAR PROCESS | Dec 12, 1990 | Abandoned |
Array
(
[id] => 2787140
[patent_doc_number] => 05100812
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/625474
[patent_app_country] => US
[patent_app_date] => 1990-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2402
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 346
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/100/05100812.pdf
[firstpage_image] =>[orig_patent_app_number] => 625474
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/625474 | Method of manufacturing semiconductor device | Dec 10, 1990 | Issued |
| 07/620624 | METHOD OF PRODUCING BIPOLAR TRANSISTOR | Dec 2, 1990 | Abandoned |
| 07/618273 | BIPOLAR TRANSISTORS, SYSTEMS AND METHODS | Nov 22, 1990 | Abandoned |
| 07/618353 | PROCESS FOR THE SIMULTANEOUS FABRICATION OF HIGH-LOW AND LOW-VOLTAGE SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT CONTAINING THE SAME, SYSTEMS AND METHODS | Nov 22, 1990 | Abandoned |
| 07/618351 | INSULATED GATE FIELD-EFFECT TRANSISTORS, SYSTEMS AND METHODS | Nov 22, 1990 | Abandoned |
| 07/617850 | VERTICAL AND LATERAL INSULATED-GATE, FIELD-EFFECT TRANSISTORS, SYSTEMS AND METHODS | Nov 20, 1990 | Abandoned |
Array
(
[id] => 2882183
[patent_doc_number] => 05108950
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Method for forming a bump electrode for a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/617399
[patent_app_country] => US
[patent_app_date] => 1990-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3144
[patent_no_of_claims] => 14
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[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/108/05108950.pdf
[firstpage_image] =>[orig_patent_app_number] => 617399
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/617399 | Method for forming a bump electrode for a semiconductor device | Nov 19, 1990 | Issued |
| 07/617464 | PROCESS FOR FABRICATING INTEGRATED CIRCUITS HAVING SHALLOW JUNCTIONS | Nov 18, 1990 | Abandoned |
Array
(
[id] => 2845156
[patent_doc_number] => 05106781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-21
[patent_title] => 'Method of establishing an interconnection level on a semiconductor device having a high integration density'
[patent_app_type] => 1
[patent_app_number] => 7/611388
[patent_app_country] => US
[patent_app_date] => 1990-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 4184
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/106/05106781.pdf
[firstpage_image] =>[orig_patent_app_number] => 611388
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/611388 | Method of establishing an interconnection level on a semiconductor device having a high integration density | Nov 4, 1990 | Issued |
Array
(
[id] => 2871398
[patent_doc_number] => 05091337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-25
[patent_title] => 'Method of manufacturing amorphous-silicon thin-film transistors'
[patent_app_type] => 1
[patent_app_number] => 7/609127
[patent_app_country] => US
[patent_app_date] => 1990-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 2112
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/091/05091337.pdf
[firstpage_image] =>[orig_patent_app_number] => 609127
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/609127 | Method of manufacturing amorphous-silicon thin-film transistors | Oct 31, 1990 | Issued |
Array
(
[id] => 2747811
[patent_doc_number] => 05030583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Method of making single crystal semiconductor substrate articles and semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/607568
[patent_app_country] => US
[patent_app_date] => 1990-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/030/05030583.pdf
[firstpage_image] =>[orig_patent_app_number] => 607568
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/607568 | Method of making single crystal semiconductor substrate articles and semiconductor device | Oct 31, 1990 | Issued |
