Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2732345 [patent_doc_number] => 05039622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'Method for manufacturing a thin-film transistor operable at high voltage' [patent_app_type] => 1 [patent_app_number] => 7/607340 [patent_app_country] => US [patent_app_date] => 1990-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2569 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/039/05039622.pdf [firstpage_image] =>[orig_patent_app_number] => 607340 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/607340
Method for manufacturing a thin-film transistor operable at high voltage Oct 30, 1990 Issued
Array ( [id] => 2781365 [patent_doc_number] => 05087581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-11 [patent_title] => 'Method of forming vertical FET device with low gate to source overlap capacitance' [patent_app_type] => 1 [patent_app_number] => 7/606674 [patent_app_country] => US [patent_app_date] => 1990-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2212 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/087/05087581.pdf [firstpage_image] =>[orig_patent_app_number] => 606674 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/606674
Method of forming vertical FET device with low gate to source overlap capacitance Oct 30, 1990 Issued
Array ( [id] => 2832480 [patent_doc_number] => 05120572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Method of fabricating electrical components in high density substrates' [patent_app_type] => 1 [patent_app_number] => 7/605806 [patent_app_country] => US [patent_app_date] => 1990-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 2844 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/120/05120572.pdf [firstpage_image] =>[orig_patent_app_number] => 605806 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/605806
Method of fabricating electrical components in high density substrates Oct 29, 1990 Issued
07/604000 METHOD AND APPARATUS FOR FORMING DIFFUSION JUNCTIONS IN SOLAR CELL SUBSTRATES Oct 23, 1990 Abandoned
Array ( [id] => 2692767 [patent_doc_number] => 05064776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-12 [patent_title] => 'Method of forming buried contact between polysilicon gate and diffusion area' [patent_app_type] => 1 [patent_app_number] => 7/592121 [patent_app_country] => US [patent_app_date] => 1990-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5983 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/064/05064776.pdf [firstpage_image] =>[orig_patent_app_number] => 592121 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/592121
Method of forming buried contact between polysilicon gate and diffusion area Oct 2, 1990 Issued
07/589354 SELF-ALIGNED COMPLEMENTARY HFETS Sep 27, 1990 Abandoned
Array ( [id] => 2846000 [patent_doc_number] => 05110760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Method of nanometer lithography' [patent_app_type] => 1 [patent_app_number] => 7/589758 [patent_app_country] => US [patent_app_date] => 1990-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3825 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/110/05110760.pdf [firstpage_image] =>[orig_patent_app_number] => 589758 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/589758
Method of nanometer lithography Sep 27, 1990 Issued
Array ( [id] => 2709168 [patent_doc_number] => 05061644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Method for fabricating self-aligned semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/587175 [patent_app_country] => US [patent_app_date] => 1990-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 4408 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/061/05061644.pdf [firstpage_image] =>[orig_patent_app_number] => 587175 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/587175
Method for fabricating self-aligned semiconductor devices Sep 19, 1990 Issued
07/585218 METHOD FOR FORMING A METAL LAYER IN A SEMICONDUCTOR DEVICE Sep 18, 1990 Abandoned
Array ( [id] => 2853269 [patent_doc_number] => 05112763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'Process for forming a Schottky barrier gate' [patent_app_type] => 1 [patent_app_number] => 7/583926 [patent_app_country] => US [patent_app_date] => 1990-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2543 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/112/05112763.pdf [firstpage_image] =>[orig_patent_app_number] => 583926 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/583926
Process for forming a Schottky barrier gate Sep 16, 1990 Issued
Array ( [id] => 2671487 [patent_doc_number] => 05073508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Method of manufacturing an integrated semiconductor circuit including a bipolar heterojunction transistor and/or buried resistors' [patent_app_type] => 1 [patent_app_number] => 7/583270 [patent_app_country] => US [patent_app_date] => 1990-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 29 [patent_no_of_words] => 4670 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073508.pdf [firstpage_image] =>[orig_patent_app_number] => 583270 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/583270
Method of manufacturing an integrated semiconductor circuit including a bipolar heterojunction transistor and/or buried resistors Sep 13, 1990 Issued
Array ( [id] => 2853290 [patent_doc_number] => 05112764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'Method for the fabrication of low leakage polysilicon thin film transistors' [patent_app_type] => 1 [patent_app_number] => 7/578106 [patent_app_country] => US [patent_app_date] => 1990-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2391 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/112/05112764.pdf [firstpage_image] =>[orig_patent_app_number] => 578106 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/578106
Method for the fabrication of low leakage polysilicon thin film transistors Sep 3, 1990 Issued
Array ( [id] => 2941725 [patent_doc_number] => 05254488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Easily manufacturable thin film transistor structures' [patent_app_type] => 1 [patent_app_number] => 7/581316 [patent_app_country] => US [patent_app_date] => 1990-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3400 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/254/05254488.pdf [firstpage_image] =>[orig_patent_app_number] => 581316 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/581316
Easily manufacturable thin film transistor structures Sep 3, 1990 Issued
Array ( [id] => 2844916 [patent_doc_number] => 05106768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'Method for the manufacture of CMOS FET by P+ maskless technique' [patent_app_type] => 1 [patent_app_number] => 7/575846 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2754 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/106/05106768.pdf [firstpage_image] =>[orig_patent_app_number] => 575846 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/575846
Method for the manufacture of CMOS FET by P+ maskless technique Aug 30, 1990 Issued
Array ( [id] => 2784330 [patent_doc_number] => 05130266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-14 [patent_title] => 'Polycide gate MOSFET process for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/573814 [patent_app_country] => US [patent_app_date] => 1990-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 3965 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/130/05130266.pdf [firstpage_image] =>[orig_patent_app_number] => 573814 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/573814
Polycide gate MOSFET process for integrated circuits Aug 27, 1990 Issued
Array ( [id] => 2926905 [patent_doc_number] => 05187118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Method of manufacturing semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/570828 [patent_app_country] => US [patent_app_date] => 1990-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 2868 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/187/05187118.pdf [firstpage_image] =>[orig_patent_app_number] => 570828 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/570828
Method of manufacturing semiconductor devices Aug 21, 1990 Issued
Array ( [id] => 2803705 [patent_doc_number] => 05147775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Method of fabricating a high-frequency bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/570958 [patent_app_country] => US [patent_app_date] => 1990-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 23 [patent_no_of_words] => 3010 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/147/05147775.pdf [firstpage_image] =>[orig_patent_app_number] => 570958 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/570958
Method of fabricating a high-frequency bipolar transistor Aug 20, 1990 Issued
Array ( [id] => 2824735 [patent_doc_number] => 05116781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-26 [patent_title] => 'Zinc diffusion process' [patent_app_type] => 1 [patent_app_number] => 7/568803 [patent_app_country] => US [patent_app_date] => 1990-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4142 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/116/05116781.pdf [firstpage_image] =>[orig_patent_app_number] => 568803 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/568803
Zinc diffusion process Aug 16, 1990 Issued
07/567606 ERASE PERFORMANCE IMPROVEMENT VIA DUAL FLOATING GATE PROCESSING Aug 14, 1990 Abandoned
Array ( [id] => 2871173 [patent_doc_number] => 05091324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Process for producing optimum intrinsic, long channel, and short channel MOS devices in VLSI structures' [patent_app_type] => 1 [patent_app_number] => 7/565384 [patent_app_country] => US [patent_app_date] => 1990-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091324.pdf [firstpage_image] =>[orig_patent_app_number] => 565384 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/565384
Process for producing optimum intrinsic, long channel, and short channel MOS devices in VLSI structures Aug 9, 1990 Issued
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