Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
07/562069 SELF-ALIGNED BIPOLAR TRANSISTOR Aug 1, 1990 Abandoned
Array ( [id] => 3064903 [patent_doc_number] => 05294559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Method of forming a vertical transistor' [patent_app_type] => 1 [patent_app_number] => 7/559756 [patent_app_country] => US [patent_app_date] => 1990-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1608 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/294/05294559.pdf [firstpage_image] =>[orig_patent_app_number] => 559756 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/559756
Method of forming a vertical transistor Jul 29, 1990 Issued
Array ( [id] => 2744933 [patent_doc_number] => 04987089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-22 [patent_title] => 'BiCMOS process and process for forming bipolar transistors on wafers also containing FETs' [patent_app_type] => 1 [patent_app_number] => 7/556907 [patent_app_country] => US [patent_app_date] => 1990-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3421 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/987/04987089.pdf [firstpage_image] =>[orig_patent_app_number] => 556907 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/556907
BiCMOS process and process for forming bipolar transistors on wafers also containing FETs Jul 22, 1990 Issued
Array ( [id] => 2670038 [patent_doc_number] => 04983534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-08 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 7/555678 [patent_app_country] => US [patent_app_date] => 1990-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1968 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/983/04983534.pdf [firstpage_image] =>[orig_patent_app_number] => 555678 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/555678
Semiconductor device and method of manufacturing the same Jul 19, 1990 Issued
Array ( [id] => 2822984 [patent_doc_number] => 05094978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Method of patterning a transparent conductor' [patent_app_type] => 1 [patent_app_number] => 7/554367 [patent_app_country] => US [patent_app_date] => 1990-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 3687 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/094/05094978.pdf [firstpage_image] =>[orig_patent_app_number] => 554367 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/554367
Method of patterning a transparent conductor Jul 18, 1990 Issued
07/548015 METHOD FOR FORMING MOS TRANSISTORS Jul 4, 1990 Abandoned
Array ( [id] => 2781327 [patent_doc_number] => 05087579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-11 [patent_title] => 'Method for fabricating an integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias' [patent_app_type] => 1 [patent_app_number] => 7/546461 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2993 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/087/05087579.pdf [firstpage_image] =>[orig_patent_app_number] => 546461 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/546461
Method for fabricating an integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias Jun 28, 1990 Issued
Array ( [id] => 2734717 [patent_doc_number] => 05077234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Planarization process utilizing three resist layers' [patent_app_type] => 1 [patent_app_number] => 7/545858 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2531 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077234.pdf [firstpage_image] =>[orig_patent_app_number] => 545858 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/545858
Planarization process utilizing three resist layers Jun 28, 1990 Issued
Array ( [id] => 2854645 [patent_doc_number] => 05166081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Method of producing a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/549589 [patent_app_country] => US [patent_app_date] => 1990-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 53 [patent_no_of_words] => 7440 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166081.pdf [firstpage_image] =>[orig_patent_app_number] => 549589 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/549589
Method of producing a bipolar transistor Jun 26, 1990 Issued
Array ( [id] => 2742121 [patent_doc_number] => 05028550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/543378 [patent_app_country] => US [patent_app_date] => 1990-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5764 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028550.pdf [firstpage_image] =>[orig_patent_app_number] => 543378 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/543378
Method of manufacturing semiconductor device Jun 25, 1990 Issued
Array ( [id] => 2771539 [patent_doc_number] => 05075241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-24 [patent_title] => 'Method of forming a recessed contact bipolar transistor and field effect device' [patent_app_type] => 1 [patent_app_number] => 7/542294 [patent_app_country] => US [patent_app_date] => 1990-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 6592 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/075/05075241.pdf [firstpage_image] =>[orig_patent_app_number] => 542294 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542294
Method of forming a recessed contact bipolar transistor and field effect device Jun 21, 1990 Issued
07/541449 METHOD FOR PLANARIZING AN INTEGRATED CIRCUIT STRUCTURE USING LOW MELTING INORGANIC MATERIAL AND FLOWING WHILE DEPOSITING Jun 20, 1990 Abandoned
Array ( [id] => 2705762 [patent_doc_number] => 05013671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'Process for reduced emitter-base capacitance in bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/541427 [patent_app_country] => US [patent_app_date] => 1990-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6983 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/013/05013671.pdf [firstpage_image] =>[orig_patent_app_number] => 541427 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/541427
Process for reduced emitter-base capacitance in bipolar transistor Jun 19, 1990 Issued
Array ( [id] => 2788555 [patent_doc_number] => 05135888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Field effect device with polycrystalline silicon channel' [patent_app_type] => 1 [patent_app_number] => 7/531014 [patent_app_country] => US [patent_app_date] => 1990-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2576 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/135/05135888.pdf [firstpage_image] =>[orig_patent_app_number] => 531014 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/531014
Field effect device with polycrystalline silicon channel May 30, 1990 Issued
Array ( [id] => 2703717 [patent_doc_number] => 05068201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-26 [patent_title] => 'Method for forming a high valued resistive load element and low resistance interconnect for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/531022 [patent_app_country] => US [patent_app_date] => 1990-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2138 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/068/05068201.pdf [firstpage_image] =>[orig_patent_app_number] => 531022 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/531022
Method for forming a high valued resistive load element and low resistance interconnect for integrated circuits May 30, 1990 Issued
Array ( [id] => 2669977 [patent_doc_number] => 05026662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-25 [patent_title] => 'Method for fabricating a semiconductor stripe laser' [patent_app_type] => 1 [patent_app_number] => 7/527692 [patent_app_country] => US [patent_app_date] => 1990-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 3386 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/026/05026662.pdf [firstpage_image] =>[orig_patent_app_number] => 527692 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/527692
Method for fabricating a semiconductor stripe laser May 23, 1990 Issued
Array ( [id] => 2733943 [patent_doc_number] => 04997788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-05 [patent_title] => 'Display device including lateral Schottky diodes' [patent_app_type] => 1 [patent_app_number] => 7/521052 [patent_app_country] => US [patent_app_date] => 1990-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2516 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/997/04997788.pdf [firstpage_image] =>[orig_patent_app_number] => 521052 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/521052
Display device including lateral Schottky diodes May 8, 1990 Issued
Array ( [id] => 2705147 [patent_doc_number] => 05001074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-19 [patent_title] => 'Methods of producing on a semi-conductor substructure a bipolar transistor, or a bipolar and a field effect transistor or a bipolar and a field effect transistor with a complementary field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/515679 [patent_app_country] => US [patent_app_date] => 1990-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4406 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/001/05001074.pdf [firstpage_image] =>[orig_patent_app_number] => 515679 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/515679
Methods of producing on a semi-conductor substructure a bipolar transistor, or a bipolar and a field effect transistor or a bipolar and a field effect transistor with a complementary field effect transistor Apr 25, 1990 Issued
Array ( [id] => 2697932 [patent_doc_number] => 04988634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-29 [patent_title] => 'Method for forming FET with a super lattice channel' [patent_app_type] => 1 [patent_app_number] => 7/512026 [patent_app_country] => US [patent_app_date] => 1990-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1582 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/988/04988634.pdf [firstpage_image] =>[orig_patent_app_number] => 512026 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/512026
Method for forming FET with a super lattice channel Apr 15, 1990 Issued
Array ( [id] => 2722759 [patent_doc_number] => 05024966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-18 [patent_title] => 'Method of forming a silicon-based semiconductor optical device mount' [patent_app_type] => 1 [patent_app_number] => 7/510338 [patent_app_country] => US [patent_app_date] => 1990-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3387 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/024/05024966.pdf [firstpage_image] =>[orig_patent_app_number] => 510338 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/510338
Method of forming a silicon-based semiconductor optical device mount Apr 15, 1990 Issued
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