Hua Jasmine Song

Array ( [id] => 2782097 [patent_doc_number] => 05164322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Method for manufacturing photoelectric conversion device with a high response speed' [patent_app_type] => 1 [patent_app_number] => 7/507526 [patent_app_country] => US [patent_app_date] => 1990-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 45 [patent_no_of_words] => 4037 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/164/05164322.pdf [firstpage_image] =>[orig_patent_app_number] => 507526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2953406 [patent_doc_number] => 05231050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-27 [patent_title] => 'Method of laser connection of a conductor to a doped region of the substrate of an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/506995 [patent_app_country] => US [patent_app_date] => 1990-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2556 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/231/05231050.pdf [firstpage_image] =>[orig_patent_app_number] => 506995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2732363 [patent_doc_number] => 05039623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/504187 [patent_app_country] => US [patent_app_date] => 1990-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 6849 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/039/05039623.pdf [firstpage_image] =>[orig_patent_app_number] => 504187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2705918 [patent_doc_number] => 04981806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-01 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/504194 [patent_app_country] => US [patent_app_date] => 1990-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 6353 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/981/04981806.pdf [firstpage_image] =>[orig_patent_app_number] => 504194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2848372 [patent_doc_number] => 05104817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'Method of forming bipolar transistor with integral base emitter load resistor' [patent_app_type] => 1 [patent_app_number] => 7/496486 [patent_app_country] => US [patent_app_date] => 1990-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 3097 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/104/05104817.pdf [firstpage_image] =>[orig_patent_app_number] => 496486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2595920 [patent_doc_number] => 04975381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-04 [patent_title] => 'Method of manufacturing super self-alignment technology bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/492488 [patent_app_country] => US [patent_app_date] => 1990-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 4552 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 485 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/975/04975381.pdf [firstpage_image] =>[orig_patent_app_number] => 492488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2745407 [patent_doc_number] => 05015600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'Method for making integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/470027 [patent_app_country] => US [patent_app_date] => 1990-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3879 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/015/05015600.pdf [firstpage_image] =>[orig_patent_app_number] => 470027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2671710 [patent_doc_number] => 05073520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Method of making a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/466915 [patent_app_country] => US [patent_app_date] => 1990-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2604 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073520.pdf [firstpage_image] =>[orig_patent_app_number] => 466915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2596458 [patent_doc_number] => 04965226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-23 [patent_title] => 'Method of forming an interconnection between conductive levels' [patent_app_type] => 1 [patent_app_number] => 7/465560 [patent_app_country] => US [patent_app_date] => 1990-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/965/04965226.pdf [firstpage_image] =>[orig_patent_app_number] => 465560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2765527 [patent_doc_number] => 05006485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-09 [patent_title] => 'Method of manufacturing an intergrated circuit including steps for forming interconnections between patterns formed at different levels' [patent_app_type] => 1 [patent_app_number] => 7/446506 [patent_app_country] => US [patent_app_date] => 1989-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 9077 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/006/05006485.pdf [firstpage_image] =>[orig_patent_app_number] => 446506 [rel_patent_id] =>[rel_patent_doc_number] =>)