Hua Jasmine Song

Array ( [id] => 2713056 [patent_doc_number] => 05053348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-01 [patent_title] => 'Fabrication of self-aligned, T-gate HEMT' [patent_app_type] => 1 [patent_app_number] => 7/444708 [patent_app_country] => US [patent_app_date] => 1989-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3926 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/053/05053348.pdf [firstpage_image] =>[orig_patent_app_number] => 444708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2765361 [patent_doc_number] => 05006476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-09 [patent_title] => 'Transistor manufacturing process using three-step base doping' [patent_app_type] => 1 [patent_app_number] => 7/440456 [patent_app_country] => US [patent_app_date] => 1989-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/006/05006476.pdf [firstpage_image] =>[orig_patent_app_number] => 440456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2734054 [patent_doc_number] => 04997794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-05 [patent_title] => 'Method of making semiconductor device comprising a capacitor and a buried passivation layer' [patent_app_type] => 1 [patent_app_number] => 7/435091 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1912 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/997/04997794.pdf [firstpage_image] =>[orig_patent_app_number] => 435091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2712813 [patent_doc_number] => 05010030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-23 [patent_title] => 'Semiconductor process using selective deposition' [patent_app_type] => 1 [patent_app_number] => 7/428721 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3593 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/010/05010030.pdf [firstpage_image] =>[orig_patent_app_number] => 428721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2757858 [patent_doc_number] => 05059546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-22 [patent_title] => 'BICMOS process for forming shallow NPN emitters and mosfet source/drains' [patent_app_type] => 1 [patent_app_number] => 7/416619 [patent_app_country] => US [patent_app_date] => 1989-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5053 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/059/05059546.pdf [firstpage_image] =>[orig_patent_app_number] => 416619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2589022 [patent_doc_number] => 04970176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-13 [patent_title] => 'Multiple step metallization process' [patent_app_type] => 1 [patent_app_number] => 7/414355 [patent_app_country] => US [patent_app_date] => 1989-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2138 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/970/04970176.pdf [firstpage_image] =>[orig_patent_app_number] => 414355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2882032 [patent_doc_number] => 05108944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/413006 [patent_app_country] => US [patent_app_date] => 1989-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 6021 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/108/05108944.pdf [firstpage_image] =>[orig_patent_app_number] => 413006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2823024 [patent_doc_number] => 05094980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Method for providing a metal-semiconductor contact' [patent_app_type] => 1 [patent_app_number] => 7/412634 [patent_app_country] => US [patent_app_date] => 1989-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2682 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/094/05094980.pdf [firstpage_image] =>[orig_patent_app_number] => 412634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2640960 [patent_doc_number] => 04939099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-03 [patent_title] => 'Process for fabricating isolated vertical bipolar and JFET transistors' [patent_app_type] => 1 [patent_app_number] => 7/411210 [patent_app_country] => US [patent_app_date] => 1989-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3282 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/939/04939099.pdf [firstpage_image] =>[orig_patent_app_number] => 411210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2669842 [patent_doc_number] => 05026655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-25 [patent_title] => 'Process of fabricating a heterojunction field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/410070 [patent_app_country] => US [patent_app_date] => 1989-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2675 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/026/05026655.pdf [firstpage_image] =>[orig_patent_app_number] => 410070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2812749 [patent_doc_number] => 05079177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-07 [patent_title] => 'Process for fabricating high performance BiCMOS circuits' [patent_app_type] => 1 [patent_app_number] => 7/409545 [patent_app_country] => US [patent_app_date] => 1989-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5863 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/079/05079177.pdf [firstpage_image] =>[orig_patent_app_number] => 409545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2714374 [patent_doc_number] => 05008211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-16 [patent_title] => 'Method for forming FET with a super lattice channel' [patent_app_type] => 1 [patent_app_number] => 7/406859 [patent_app_country] => US [patent_app_date] => 1989-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1584 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/008/05008211.pdf [firstpage_image] =>[orig_patent_app_number] => 406859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2714290 [patent_doc_number] => 05008207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-16 [patent_title] => 'Method of fabricating a narrow base transistor' [patent_app_type] => 1 [patent_app_number] => 7/405508 [patent_app_country] => US [patent_app_date] => 1989-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 3646 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/008/05008207.pdf [firstpage_image] =>[orig_patent_app_number] => 405508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2733753 [patent_doc_number] => 04997778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-05 [patent_title] => 'Process for forming a self-aligned FET having a T-shaped gate structure' [patent_app_type] => 1 [patent_app_number] => 7/402607 [patent_app_country] => US [patent_app_date] => 1989-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2706 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/997/04997778.pdf [firstpage_image] =>[orig_patent_app_number] => 402607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2693686 [patent_doc_number] => 05019524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-28 [patent_title] => 'Method of manufacturing a heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/401506 [patent_app_country] => US [patent_app_date] => 1989-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2182 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/019/05019524.pdf [firstpage_image] =>[orig_patent_app_number] => 401506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2742401 [patent_doc_number] => 05028565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Process for CVD deposition of tungsten layer on semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 7/398653 [patent_app_country] => US [patent_app_date] => 1989-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3197 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028565.pdf [firstpage_image] =>[orig_patent_app_number] => 398653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2742165 [patent_doc_number] => 05028552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Method of manufacturing insulated-gate type field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/395356 [patent_app_country] => US [patent_app_date] => 1989-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 24 [patent_no_of_words] => 3365 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028552.pdf [firstpage_image] =>[orig_patent_app_number] => 395356 [rel_patent_id] =>[rel_patent_doc_number] =>)