
Hua Jasmine Song
Examiner (ID: 11195)
| Most Active Art Unit | 2133 |
| Art Unit(s) | 2189, 2131, 2138, 2187, 2188, 2133 |
| Total Applications | 1391 |
| Issued Applications | 1254 |
| Pending Applications | 70 |
| Abandoned Applications | 80 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17809333
[patent_doc_number] => 20220261168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => INFINITE MEMORY FABRIC HARDWARE IMPLEMENTATION WITH ROUTER
[patent_app_type] => utility
[patent_app_number] => 17/582416
[patent_app_country] => US
[patent_app_date] => 2022-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33903
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582416
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/582416 | Infinite memory fabric hardware implementation with router | Jan 23, 2022 | Issued |
Array
(
[id] => 19458955
[patent_doc_number] => 12099444
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-24
[patent_title] => Cat aware loads and software prefetches
[patent_app_type] => utility
[patent_app_number] => 17/581616
[patent_app_country] => US
[patent_app_date] => 2022-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 7039
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581616
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/581616 | Cat aware loads and software prefetches | Jan 20, 2022 | Issued |
Array
(
[id] => 17581254
[patent_doc_number] => 20220138109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => CONTINUOUS READ WITH MULTIPLE READ COMMANDS
[patent_app_type] => utility
[patent_app_number] => 17/579428
[patent_app_country] => US
[patent_app_date] => 2022-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10865
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579428
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/579428 | Continuous read with multiple read commands | Jan 18, 2022 | Issued |
Array
(
[id] => 17763514
[patent_doc_number] => 20220237126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => PAGE TABLE MANAGER
[patent_app_type] => utility
[patent_app_number] => 17/576398
[patent_app_country] => US
[patent_app_date] => 2022-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8302
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576398
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/576398 | Page table manager | Jan 13, 2022 | Issued |
Array
(
[id] => 18780742
[patent_doc_number] => 11822472
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-21
[patent_title] => Memory management unit for multi-threaded architecture
[patent_app_type] => utility
[patent_app_number] => 17/575521
[patent_app_country] => US
[patent_app_date] => 2022-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 10053
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575521
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/575521 | Memory management unit for multi-threaded architecture | Jan 12, 2022 | Issued |
Array
(
[id] => 19061687
[patent_doc_number] => 11940921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => Bounding box prefetcher
[patent_app_type] => utility
[patent_app_number] => 17/570452
[patent_app_country] => US
[patent_app_date] => 2022-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 13259
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570452
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/570452 | Bounding box prefetcher | Jan 6, 2022 | Issued |
Array
(
[id] => 19905423
[patent_doc_number] => 12282428
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-22
[patent_title] => Selective speculative prefetch requests for a last-level cache
[patent_app_type] => utility
[patent_app_number] => 17/564141
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4577
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564141
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/564141 | Selective speculative prefetch requests for a last-level cache | Dec 27, 2021 | Issued |
Array
(
[id] => 19375385
[patent_doc_number] => 12066950
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-20
[patent_title] => Approach for managing near-memory processing commands and non-near-memory processing commands in a memory controller
[patent_app_type] => utility
[patent_app_number] => 17/561454
[patent_app_country] => US
[patent_app_date] => 2021-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 7448
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561454
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/561454 | Approach for managing near-memory processing commands and non-near-memory processing commands in a memory controller | Dec 22, 2021 | Issued |
Array
(
[id] => 19340602
[patent_doc_number] => 12050792
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Optimizing memory to storage capacity division on a DC persistent memory module (DCPMM) in mixed mode
[patent_app_type] => utility
[patent_app_number] => 17/561343
[patent_app_country] => US
[patent_app_date] => 2021-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5643
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561343
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/561343 | Optimizing memory to storage capacity division on a DC persistent memory module (DCPMM) in mixed mode | Dec 22, 2021 | Issued |
Array
(
[id] => 18454345
[patent_doc_number] => 20230195625
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => Data Routing for Efficient Decompression of Compressed Data Stored in a Cache
[patent_app_type] => utility
[patent_app_number] => 17/557815
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8476
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557815
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/557815 | Data routing for efficient decompression of compressed data stored in a cache | Dec 20, 2021 | Issued |
Array
(
[id] => 17659326
[patent_doc_number] => 20220179791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => INVALIDATION AND REFRESH OF MULTI-TIER DISTRIBUTED CACHES
[patent_app_type] => utility
[patent_app_number] => 17/544392
[patent_app_country] => US
[patent_app_date] => 2021-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12645
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544392
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/544392 | Invalidation and refresh of multi-tier distributed caches | Dec 6, 2021 | Issued |
Array
(
[id] => 17659334
[patent_doc_number] => 20220179799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => HETEROGENOUS-LATENCY MEMORY OPTIMIZATION
[patent_app_type] => utility
[patent_app_number] => 17/543449
[patent_app_country] => US
[patent_app_date] => 2021-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8793
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543449
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/543449 | Heterogenous-latency memory optimization | Dec 5, 2021 | Issued |
Array
(
[id] => 19522658
[patent_doc_number] => 12124381
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Hardware translation request retry mechanism
[patent_app_type] => utility
[patent_app_number] => 17/529499
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6642
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529499
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529499 | Hardware translation request retry mechanism | Nov 17, 2021 | Issued |
Array
(
[id] => 18734748
[patent_doc_number] => 11803479
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Caching streams of memory requests
[patent_app_type] => utility
[patent_app_number] => 17/455343
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7164
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455343
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/455343 | Caching streams of memory requests | Nov 16, 2021 | Issued |
Array
(
[id] => 18734748
[patent_doc_number] => 11803479
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Caching streams of memory requests
[patent_app_type] => utility
[patent_app_number] => 17/455343
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7164
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455343
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/455343 | Caching streams of memory requests | Nov 16, 2021 | Issued |
Array
(
[id] => 18734748
[patent_doc_number] => 11803479
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Caching streams of memory requests
[patent_app_type] => utility
[patent_app_number] => 17/455343
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7164
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455343
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/455343 | Caching streams of memory requests | Nov 16, 2021 | Issued |
Array
(
[id] => 18734748
[patent_doc_number] => 11803479
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Caching streams of memory requests
[patent_app_type] => utility
[patent_app_number] => 17/455343
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7164
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455343
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/455343 | Caching streams of memory requests | Nov 16, 2021 | Issued |
Array
(
[id] => 18378161
[patent_doc_number] => 20230153248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => DATA AUTO-RELOCATION IN AN INTEGRATED MEMORY ASSEMBLY
[patent_app_type] => utility
[patent_app_number] => 17/527792
[patent_app_country] => US
[patent_app_date] => 2021-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18719
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527792
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/527792 | Data auto-relocation in an integrated memory assembly | Nov 15, 2021 | Issued |
Array
(
[id] => 17462216
[patent_doc_number] => 20220075521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING A CONTROL CIRCUIT AND AT LEAST TWO MEMORY CELL ARRAYS
[patent_app_type] => utility
[patent_app_number] => 17/527851
[patent_app_country] => US
[patent_app_date] => 2021-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12839
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527851
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/527851 | Semiconductor memory device including a control circuit and at least two memory cell arrays | Nov 15, 2021 | Issued |
Array
(
[id] => 18519891
[patent_doc_number] => 11709782
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-25
[patent_title] => Memory address translation
[patent_app_type] => utility
[patent_app_number] => 17/512888
[patent_app_country] => US
[patent_app_date] => 2021-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 7928
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512888
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/512888 | Memory address translation | Oct 27, 2021 | Issued |