Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2632450 [patent_doc_number] => 04977105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-11 [patent_title] => 'Method for manufacturing interconnection structure in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/391309 [patent_app_country] => US [patent_app_date] => 1989-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5646 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/977/04977105.pdf [firstpage_image] =>[orig_patent_app_number] => 391309 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/391309
Method for manufacturing interconnection structure in semiconductor device Aug 8, 1989 Issued
07/385207 BUMP ELECTRODE STRUCTURE OF A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE SAME Jul 24, 1989 Abandoned
07/382553 METHOD FOR FORMING MULTILAYER WIRINGS ON A SEMICONDUCTOR DEVICE Jul 18, 1989 Abandoned
Array ( [id] => 2679942 [patent_doc_number] => 05066613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-19 [patent_title] => 'Process for making semiconductor-on-insulator device interconnects' [patent_app_type] => 1 [patent_app_number] => 7/380175 [patent_app_country] => US [patent_app_date] => 1989-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4367 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/066/05066613.pdf [firstpage_image] =>[orig_patent_app_number] => 380175 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/380175
Process for making semiconductor-on-insulator device interconnects Jul 12, 1989 Issued
Array ( [id] => 2845176 [patent_doc_number] => 05106782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/378627 [patent_app_country] => US [patent_app_date] => 1989-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3553 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/106/05106782.pdf [firstpage_image] =>[orig_patent_app_number] => 378627 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/378627
Method of manufacturing a semiconductor device Jul 11, 1989 Issued
Array ( [id] => 2769730 [patent_doc_number] => 04985367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-15 [patent_title] => 'Method of manufacturing a lateral transistor' [patent_app_type] => 1 [patent_app_number] => 7/379675 [patent_app_country] => US [patent_app_date] => 1989-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3072 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/985/04985367.pdf [firstpage_image] =>[orig_patent_app_number] => 379675 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/379675
Method of manufacturing a lateral transistor Jul 10, 1989 Issued
07/377731 SEMICONDUCTOR DEVICE HAVING WIRING ELECTRODES Jul 9, 1989 Abandoned
07/376060 METHOD OF ESTABLISHING AN INTERCONNECTION LEVEL ON A SEMICONDUCTOR DEVICE HAVING A HIGH INTEGRATION DENSITY Jul 4, 1989 Abandoned
Array ( [id] => 2602410 [patent_doc_number] => 04948743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-14 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/373102 [patent_app_country] => US [patent_app_date] => 1989-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2156 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/948/04948743.pdf [firstpage_image] =>[orig_patent_app_number] => 373102 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/373102
Method of manufacturing a semiconductor device Jun 28, 1989 Issued
Array ( [id] => 2644818 [patent_doc_number] => 04980305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-25 [patent_title] => 'Method of manufacturing bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/372424 [patent_app_country] => US [patent_app_date] => 1989-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4624 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 527 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/980/04980305.pdf [firstpage_image] =>[orig_patent_app_number] => 372424 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/372424
Method of manufacturing bipolar transistor Jun 25, 1989 Issued
Array ( [id] => 2632321 [patent_doc_number] => 04977098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-11 [patent_title] => 'Method of forming a self-aligned bipolar transistor using amorphous silicon' [patent_app_type] => 1 [patent_app_number] => 7/370885 [patent_app_country] => US [patent_app_date] => 1989-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3131 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/977/04977098.pdf [firstpage_image] =>[orig_patent_app_number] => 370885 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/370885
Method of forming a self-aligned bipolar transistor using amorphous silicon Jun 22, 1989 Issued
Array ( [id] => 2743152 [patent_doc_number] => 05011786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Method of manufacturing a hybrid circuit element' [patent_app_type] => 1 [patent_app_number] => 7/370940 [patent_app_country] => US [patent_app_date] => 1989-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2822 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/011/05011786.pdf [firstpage_image] =>[orig_patent_app_number] => 370940 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/370940
Method of manufacturing a hybrid circuit element Jun 22, 1989 Issued
Array ( [id] => 2754303 [patent_doc_number] => 05043295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-27 [patent_title] => 'Method of forming an IC chip with self-aligned thin film resistors' [patent_app_type] => 1 [patent_app_number] => 7/368825 [patent_app_country] => US [patent_app_date] => 1989-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 2949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/043/05043295.pdf [firstpage_image] =>[orig_patent_app_number] => 368825 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/368825
Method of forming an IC chip with self-aligned thin film resistors Jun 19, 1989 Issued
Array ( [id] => 2584440 [patent_doc_number] => 04932872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-12 [patent_title] => 'Method for fabricating X-ray masks' [patent_app_type] => 1 [patent_app_number] => 7/366937 [patent_app_country] => US [patent_app_date] => 1989-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1097 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/932/04932872.pdf [firstpage_image] =>[orig_patent_app_number] => 366937 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/366937
Method for fabricating X-ray masks Jun 15, 1989 Issued
07/365968 METHODS OF PRODUCING ON A SEMI-CONDUCTOR SUBSTRUCTURE A BIPOLAR TRANSISTOR, OR A BIPOLAR AND A FIELD EFFECT TRANSISTOR OR A BIPOLAR AND A FIELD EFFECT TRANSISTOR WITH A COMPLEMENTARY FIELD EFFECT TRANSISTOR Jun 12, 1989 Abandoned
Array ( [id] => 2706521 [patent_doc_number] => 05055425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-08 [patent_title] => 'Stacked solid via formation in integrated circuit systems' [patent_app_type] => 1 [patent_app_number] => 7/360828 [patent_app_country] => US [patent_app_date] => 1989-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 3818 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/055/05055425.pdf [firstpage_image] =>[orig_patent_app_number] => 360828 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/360828
Stacked solid via formation in integrated circuit systems May 31, 1989 Issued
Array ( [id] => 2865785 [patent_doc_number] => 05162244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Bipolar transistor and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 7/358023 [patent_app_country] => US [patent_app_date] => 1989-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2734 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/162/05162244.pdf [firstpage_image] =>[orig_patent_app_number] => 358023 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/358023
Bipolar transistor and manufacturing method thereof May 30, 1989 Issued
Array ( [id] => 2693835 [patent_doc_number] => 05019533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-28 [patent_title] => 'Thermal treatment of silicon integrated circuit chips to prevent and heal voids in aluminum metallization' [patent_app_type] => 1 [patent_app_number] => 7/357758 [patent_app_country] => US [patent_app_date] => 1989-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4865 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/019/05019533.pdf [firstpage_image] =>[orig_patent_app_number] => 357758 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/357758
Thermal treatment of silicon integrated circuit chips to prevent and heal voids in aluminum metallization May 25, 1989 Issued
Array ( [id] => 2623819 [patent_doc_number] => 04956312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-11 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/354001 [patent_app_country] => US [patent_app_date] => 1989-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5507 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/956/04956312.pdf [firstpage_image] =>[orig_patent_app_number] => 354001 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/354001
Method of manufacturing a semiconductor device May 18, 1989 Issued
Array ( [id] => 2866329 [patent_doc_number] => 05096842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Method of fabricating bipolar transistor using self-aligned polysilicon technology' [patent_app_type] => 1 [patent_app_number] => 7/350860 [patent_app_country] => US [patent_app_date] => 1989-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 44 [patent_no_of_words] => 8616 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/096/05096842.pdf [firstpage_image] =>[orig_patent_app_number] => 350860 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/350860
Method of fabricating bipolar transistor using self-aligned polysilicon technology May 8, 1989 Issued
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