Huan Hoang

Array ( [id] => 6724148 [patent_doc_number] => 20030206460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Storage device counting error correction' [patent_app_type] => new [patent_app_number] => 10/430345 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3718 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20030206460.pdf [firstpage_image] =>[orig_patent_app_number] => 10430345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1130950 [patent_doc_number] => 06791880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Non-volatile memory read circuit with end of life simulation' [patent_app_type] => B1 [patent_app_number] => 10/431320 [patent_app_country] => US [patent_app_date] => 2003-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3195 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791880.pdf [firstpage_image] =>[orig_patent_app_number] => 10431320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6824478 [patent_doc_number] => 20030235100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Method for reducing spurious erasing during programming of a nonvolatile NROM' [patent_app_type] => new [patent_app_number] => 10/426924 [patent_app_country] => US [patent_app_date] => 2003-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4648 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235100.pdf [firstpage_image] =>[orig_patent_app_number] => 10426924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1057918 [patent_doc_number] => 06856532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Offset compensated sensing for magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 10/422850 [patent_app_country] => US [patent_app_date] => 2003-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4398 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856532.pdf [firstpage_image] =>[orig_patent_app_number] => 10422850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1149330 [patent_doc_number] => 06778428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Magnetic random access memory (MRAM) cells including an access transistor and a bit line that are connected to a terminal of a magnetic resistor, and methods of operating same' [patent_app_type] => B2 [patent_app_number] => 10/421322 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3953 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/778/06778428.pdf [firstpage_image] =>[orig_patent_app_number] => 10421322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 957026 [patent_doc_number] => 06956780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Semiconductor memory device having direct sense amplifier implemented in hierarchical input/output line architecture' [patent_app_type] => utility [patent_app_number] => 10/417098 [patent_app_country] => US [patent_app_date] => 2003-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6388 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/956/06956780.pdf [firstpage_image] =>[orig_patent_app_number] => 10417098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7418904 [patent_doc_number] => 20040208057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Method of programming dual cell memory device to store multiple data states per cell' [patent_app_type] => new [patent_app_number] => 10/413800 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6767 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20040208057.pdf [firstpage_image] =>[orig_patent_app_number] => 10413800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6824473 [patent_doc_number] => 20030235095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Semiconductor memory device with an improved memory cell structure and method of operating the same' [patent_app_type] => new [patent_app_number] => 10/411700 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16616 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235095.pdf [firstpage_image] =>[orig_patent_app_number] => 10411700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6808168 [patent_doc_number] => 20030198107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Method of checking the state of a capacitor fuse in which the voltage applied to the capacitor fuse is the same level as voltage applied to memory cells' [patent_app_type] => new [patent_app_number] => 10/410124 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5280 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20030198107.pdf [firstpage_image] =>[orig_patent_app_number] => 10410124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1038976 [patent_doc_number] => 06873561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Semiconductor memory device operating with low current consumption' [patent_app_type] => utility [patent_app_number] => 10/409120 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 21288 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873561.pdf [firstpage_image] =>[orig_patent_app_number] => 10409120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1067416 [patent_doc_number] => 06847571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Use of redundant memory cells to manufacture cost efficient drams with reduced self refresh current capability' [patent_app_type] => utility [patent_app_number] => 10/406320 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1760 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/847/06847571.pdf [firstpage_image] =>[orig_patent_app_number] => 10406320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1104521 [patent_doc_number] => 06816401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Static random access memory (SRAM) without precharge circuitry' [patent_app_type] => B2 [patent_app_number] => 10/406526 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4575 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816401.pdf [firstpage_image] =>[orig_patent_app_number] => 10406526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 959444 [patent_doc_number] => 06954392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Method for reducing power consumption when sensing a resistive memory' [patent_app_type] => utility [patent_app_number] => 10/400620 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4219 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954392.pdf [firstpage_image] =>[orig_patent_app_number] => 10400620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7247388 [patent_doc_number] => 20050073893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Memory bit line leakage repair' [patent_app_type] => utility [patent_app_number] => 10/403101 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073893.pdf [firstpage_image] =>[orig_patent_app_number] => 10403101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1029521 [patent_doc_number] => 06882570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Power detecting circuit and method for stable power-on reading of flash memory device using the same' [patent_app_type] => utility [patent_app_number] => 10/402758 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6895 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882570.pdf [firstpage_image] =>[orig_patent_app_number] => 10402758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1106392 [patent_doc_number] => 06817003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Short edge management in rule based OPC' [patent_app_type] => B2 [patent_app_number] => 10/402079 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 4564 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/817/06817003.pdf [firstpage_image] =>[orig_patent_app_number] => 10402079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6724136 [patent_doc_number] => 20030206448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Sense amplifier enable signal generating circuits having process tracking capability and semiconductor memory devices including the same' [patent_app_type] => new [patent_app_number] => 10/392423 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5288 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20030206448.pdf [firstpage_image] =>[orig_patent_app_number] => 10392423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7379969 [patent_doc_number] => 20040179390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'CHALCOGENIDE GLASS CONSTANT CURRENT DEVICE, AND ITS METHOD OF FABRICATION AND OPERATION' [patent_app_type] => new [patent_app_number] => 10/386028 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9295 [patent_no_of_claims] => 180 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20040179390.pdf [firstpage_image] =>[orig_patent_app_number] => 10386028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1174112 [patent_doc_number] => 06757198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Method for operating a non-volatile memory' [patent_app_type] => B2 [patent_app_number] => 10/387712 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4198 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757198.pdf [firstpage_image] =>[orig_patent_app_number] => 10387712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1163728 [patent_doc_number] => 06765825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Differential nor memory cell having two floating gate transistors' [patent_app_type] => B1 [patent_app_number] => 10/387824 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765825.pdf [firstpage_image] =>[orig_patent_app_number] => 10387824 [rel_patent_id] =>[rel_patent_doc_number] =>)