Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6808164 [patent_doc_number] => 20030198103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/385506 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7580 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20030198103.pdf [firstpage_image] =>[orig_patent_app_number] => 10385506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/385506
Non-volatile semiconductor memory device Mar 11, 2003 Issued
Array ( [id] => 980449 [patent_doc_number] => 06930943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Methods, circuits, and systems for refreshing memory cells in a memory device that have different refresh periods' [patent_app_type] => utility [patent_app_number] => 10/383262 [patent_app_country] => US [patent_app_date] => 2003-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5067 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930943.pdf [firstpage_image] =>[orig_patent_app_number] => 10383262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/383262
Methods, circuits, and systems for refreshing memory cells in a memory device that have different refresh periods Mar 6, 2003 Issued
Array ( [id] => 7131893 [patent_doc_number] => 20040042311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/379563 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7446 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042311.pdf [firstpage_image] =>[orig_patent_app_number] => 10379563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379563
Semiconductor memory Mar 5, 2003 Issued
Array ( [id] => 1038964 [patent_doc_number] => 06873556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Semiconductor memory device with test mode and testing method thereof' [patent_app_type] => utility [patent_app_number] => 10/377596 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5114 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873556.pdf [firstpage_image] =>[orig_patent_app_number] => 10377596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/377596
Semiconductor memory device with test mode and testing method thereof Mar 3, 2003 Issued
Array ( [id] => 7398384 [patent_doc_number] => 20040174762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Deep power down switch for memory device' [patent_app_type] => new [patent_app_number] => 10/378472 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3135 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20040174762.pdf [firstpage_image] =>[orig_patent_app_number] => 10378472 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/378472
Deep power down switch for memory device Mar 2, 2003 Issued
Array ( [id] => 6950950 [patent_doc_number] => 20050226044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Semiconductor storage' [patent_app_type] => utility [patent_app_number] => 10/506322 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16491 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20050226044.pdf [firstpage_image] =>[orig_patent_app_number] => 10506322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/506322
Semiconductor storage Mar 2, 2003 Issued
Array ( [id] => 1064780 [patent_doc_number] => 06850435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/373920 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 46 [patent_no_of_words] => 30150 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/850/06850435.pdf [firstpage_image] =>[orig_patent_app_number] => 10373920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/373920
Nonvolatile semiconductor memory Feb 26, 2003 Issued
Array ( [id] => 1158340 [patent_doc_number] => 06771541 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method and apparatus for providing row redundancy in nonvolatile semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 10/375556 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7462 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771541.pdf [firstpage_image] =>[orig_patent_app_number] => 10375556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/375556
Method and apparatus for providing row redundancy in nonvolatile semiconductor memory Feb 24, 2003 Issued
Array ( [id] => 7434022 [patent_doc_number] => 20040008567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Threshold voltage adjustment method of non-volatile semiconductor memory device and non-volatile semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/369496 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20040008567.pdf [firstpage_image] =>[orig_patent_app_number] => 10369496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/369496
Threshold voltage adjustment method of non-volatile semiconductor memory device and non-volatile semiconductor memory device Feb 20, 2003 Issued
Array ( [id] => 7311297 [patent_doc_number] => 20040032790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Semiconductor memory device with efficient buffer control for data buses' [patent_app_type] => new [patent_app_number] => 10/369562 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4861 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20040032790.pdf [firstpage_image] =>[orig_patent_app_number] => 10369562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/369562
Semiconductor memory device with efficient buffer control for data buses Feb 20, 2003 Issued
Array ( [id] => 6804127 [patent_doc_number] => 20030231521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Semiconductor memory device and semiconductor device' [patent_app_type] => new [patent_app_number] => 10/369660 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16692 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20030231521.pdf [firstpage_image] =>[orig_patent_app_number] => 10369660 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/369660
Semiconductor memory device and semiconductor device Feb 20, 2003 Issued
Array ( [id] => 7474124 [patent_doc_number] => 20040168021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Associative memory having a mask function for use in a network router' [patent_app_type] => new [patent_app_number] => 10/369822 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 22068 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20040168021.pdf [firstpage_image] =>[orig_patent_app_number] => 10369822 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/369822
Associative memory having a mask function for use in a network router Feb 19, 2003 Issued
Array ( [id] => 7360474 [patent_doc_number] => 20040004900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Semiconductor integrated circuit device with embedded synchronous memory precisely operating in synchronization with high speed clock' [patent_app_type] => new [patent_app_number] => 10/368480 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 20275 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004900.pdf [firstpage_image] =>[orig_patent_app_number] => 10368480 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/368480
Semiconductor integrated circuit device with embedded synchronous memory precisely operating in synchronization with high speed clock Feb 19, 2003 Issued
Array ( [id] => 959438 [patent_doc_number] => 06954386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Boosted potential generation circuit and control method' [patent_app_type] => utility [patent_app_number] => 10/372000 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 12297 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954386.pdf [firstpage_image] =>[orig_patent_app_number] => 10372000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/372000
Boosted potential generation circuit and control method Feb 19, 2003 Issued
Array ( [id] => 1199355 [patent_doc_number] => 06728152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Sense amplifier for reduction of access device leakage' [patent_app_type] => B2 [patent_app_number] => 10/369834 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6265 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728152.pdf [firstpage_image] =>[orig_patent_app_number] => 10369834 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/369834
Sense amplifier for reduction of access device leakage Feb 17, 2003 Issued
Array ( [id] => 383911 [patent_doc_number] => 07307865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Integrated read-only memory, method for operating said read-only memory and corresponding production method' [patent_app_type] => utility [patent_app_number] => 10/505320 [patent_app_country] => US [patent_app_date] => 2003-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4362 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307865.pdf [firstpage_image] =>[orig_patent_app_number] => 10505320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/505320
Integrated read-only memory, method for operating said read-only memory and corresponding production method Feb 16, 2003 Issued
Array ( [id] => 7417283 [patent_doc_number] => 20040160251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'High density magnetic RAM and array architecture using a one transistor, one diode, and one MTJ cell' [patent_app_type] => new [patent_app_number] => 10/366498 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4371 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160251.pdf [firstpage_image] =>[orig_patent_app_number] => 10366498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366498
High density magnetic RAM and array architecture using a one transistor, one diode, and one MTJ cell Feb 12, 2003 Issued
Array ( [id] => 545025 [patent_doc_number] => 07173846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Magnetic RAM and array architecture using a two transistor, one MTJ cell' [patent_app_type] => utility [patent_app_number] => 10/366499 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4169 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173846.pdf [firstpage_image] =>[orig_patent_app_number] => 10366499 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366499
Magnetic RAM and array architecture using a two transistor, one MTJ cell Feb 12, 2003 Issued
Array ( [id] => 1023639 [patent_doc_number] => 06888751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/364342 [patent_app_country] => US [patent_app_date] => 2003-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 11758 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888751.pdf [firstpage_image] =>[orig_patent_app_number] => 10364342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364342
Nonvolatile semiconductor memory device Feb 11, 2003 Issued
Array ( [id] => 7225362 [patent_doc_number] => 20040156228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'High density beta ratio independent core cell' [patent_app_type] => new [patent_app_number] => 10/364283 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6816 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20040156228.pdf [firstpage_image] =>[orig_patent_app_number] => 10364283 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364283
High density beta ratio independent core cell Feb 9, 2003 Abandoned
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