Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1135843 [patent_doc_number] => 06788615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'System and method for low area self-timing in memory devices' [patent_app_type] => B2 [patent_app_number] => 10/364720 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788615.pdf [firstpage_image] =>[orig_patent_app_number] => 10364720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364720
System and method for low area self-timing in memory devices Feb 9, 2003 Issued
Array ( [id] => 6833705 [patent_doc_number] => 20030161250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Memory device having reduced layout area' [patent_app_type] => new [patent_app_number] => 10/361322 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2760 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20030161250.pdf [firstpage_image] =>[orig_patent_app_number] => 10361322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361322
Memory device having reduced layout area Feb 9, 2003 Issued
Array ( [id] => 7626087 [patent_doc_number] => 06768679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Selection circuit for accurate memory read operations' [patent_app_type] => B1 [patent_app_number] => 10/361378 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5995 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768679.pdf [firstpage_image] =>[orig_patent_app_number] => 10361378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361378
Selection circuit for accurate memory read operations Feb 9, 2003 Issued
Array ( [id] => 7386274 [patent_doc_number] => 20040037140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Sense amplifier drive circuits responsive to predecoded column addresses and methods for operating the same' [patent_app_type] => new [patent_app_number] => 10/361320 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5652 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037140.pdf [firstpage_image] =>[orig_patent_app_number] => 10361320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361320
Sense amplifier drive circuits responsive to predecoded column addresses and methods for operating the same Feb 9, 2003 Issued
Array ( [id] => 7610499 [patent_doc_number] => 06842359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Content addressable memory device having an operation mode setting means' [patent_app_type] => utility [patent_app_number] => 10/360924 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9397 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842359.pdf [firstpage_image] =>[orig_patent_app_number] => 10360924 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360924
Content addressable memory device having an operation mode setting means Feb 9, 2003 Issued
Array ( [id] => 1122873 [patent_doc_number] => 06798697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/360586 [patent_app_country] => US [patent_app_date] => 2003-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 11790 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798697.pdf [firstpage_image] =>[orig_patent_app_number] => 10360586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360586
Non-volatile semiconductor memory device Feb 5, 2003 Issued
Array ( [id] => 1131006 [patent_doc_number] => 06791889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Double data rate memory interface' [patent_app_type] => B2 [patent_app_number] => 10/358452 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791889.pdf [firstpage_image] =>[orig_patent_app_number] => 10358452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358452
Double data rate memory interface Feb 3, 2003 Issued
Array ( [id] => 1191110 [patent_doc_number] => 06735114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method of improving dynamic reference tracking for flash memory unit' [patent_app_type] => B1 [patent_app_number] => 10/357879 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7733 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735114.pdf [firstpage_image] =>[orig_patent_app_number] => 10357879 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/357879
Method of improving dynamic reference tracking for flash memory unit Feb 3, 2003 Issued
Array ( [id] => 6828562 [patent_doc_number] => 20030179620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/356482 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4857 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20030179620.pdf [firstpage_image] =>[orig_patent_app_number] => 10356482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356482
Semiconductor memory device Feb 2, 2003 Issued
Array ( [id] => 1158370 [patent_doc_number] => 06771545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array' [patent_app_type] => B1 [patent_app_number] => 10/353558 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6938 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771545.pdf [firstpage_image] =>[orig_patent_app_number] => 10353558 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353558
Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array Jan 28, 2003 Issued
Array ( [id] => 1074610 [patent_doc_number] => 06839278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Highly-integrated flash memory and mask ROM array architecture' [patent_app_type] => utility [patent_app_number] => 10/353584 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 7963 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839278.pdf [firstpage_image] =>[orig_patent_app_number] => 10353584 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353584
Highly-integrated flash memory and mask ROM array architecture Jan 28, 2003 Issued
Array ( [id] => 7352380 [patent_doc_number] => 20040012998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND' [patent_app_type] => new [patent_app_number] => 10/353570 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20040012998.pdf [firstpage_image] =>[orig_patent_app_number] => 10353570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353570
Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND Jan 27, 2003 Issued
Array ( [id] => 7433878 [patent_doc_number] => 20040008546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line' [patent_app_type] => new [patent_app_number] => 10/351528 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2789 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20040008546.pdf [firstpage_image] =>[orig_patent_app_number] => 10351528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/351528
Circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line Jan 26, 2003 Issued
Array ( [id] => 6850354 [patent_doc_number] => 20030142556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Differential flash memory programming technique' [patent_app_type] => new [patent_app_number] => 10/349055 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1878 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20030142556.pdf [firstpage_image] =>[orig_patent_app_number] => 10349055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349055
Differential flash memory programming technique Jan 21, 2003 Issued
Array ( [id] => 7306346 [patent_doc_number] => 20040141374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'NONVOLATILE MEMORY INTEGRATED CIRCUIT HAVING VOLATILE UTILITY AND BUFFER MEMORIES, AND METHOD OF OPERATION THEREOF' [patent_app_type] => new [patent_app_number] => 10/349384 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9638 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20040141374.pdf [firstpage_image] =>[orig_patent_app_number] => 10349384 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349384
Nonvolatile memory integrated circuit having volatile utility and buffer memories, and method of operation thereof Jan 20, 2003 Issued
Array ( [id] => 6795670 [patent_doc_number] => 20030174543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Asynchronous semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/345353 [patent_app_country] => US [patent_app_date] => 2003-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7357 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20030174543.pdf [firstpage_image] =>[orig_patent_app_number] => 10345353 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/345353
Asynchronous semiconductor memory device Jan 15, 2003 Issued
Array ( [id] => 1095536 [patent_doc_number] => 06826066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Semiconductor memory module' [patent_app_type] => B2 [patent_app_number] => 10/341358 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 10952 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826066.pdf [firstpage_image] =>[orig_patent_app_number] => 10341358 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341358
Semiconductor memory module Jan 13, 2003 Issued
Array ( [id] => 7610471 [patent_doc_number] => 06842387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method and circuit for repairing nonvolatile ferroelectric memory device' [patent_app_type] => utility [patent_app_number] => 10/339458 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 36 [patent_no_of_words] => 18467 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842387.pdf [firstpage_image] =>[orig_patent_app_number] => 10339458 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339458
Method and circuit for repairing nonvolatile ferroelectric memory device Jan 9, 2003 Issued
Array ( [id] => 1091190 [patent_doc_number] => 06829161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'Magnetostatically coupled magnetic elements utilizing spin transfer and an MRAM device using the magnetic element' [patent_app_type] => B2 [patent_app_number] => 10/339962 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11160 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829161.pdf [firstpage_image] =>[orig_patent_app_number] => 10339962 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339962
Magnetostatically coupled magnetic elements utilizing spin transfer and an MRAM device using the magnetic element Jan 9, 2003 Issued
Array ( [id] => 964914 [patent_doc_number] => 06950336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Method and apparatus for emulating an electrically erasable programmable read only memory (EEPROM) using non-volatile floating gate memory cells' [patent_app_type] => utility [patent_app_number] => 10/340342 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7117 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950336.pdf [firstpage_image] =>[orig_patent_app_number] => 10340342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/340342
Method and apparatus for emulating an electrically erasable programmable read only memory (EEPROM) using non-volatile floating gate memory cells Jan 9, 2003 Issued
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