
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1135843
[patent_doc_number] => 06788615
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-07
[patent_title] => 'System and method for low area self-timing in memory devices'
[patent_app_type] => B2
[patent_app_number] => 10/364720
[patent_app_country] => US
[patent_app_date] => 2003-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 6038
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/788/06788615.pdf
[firstpage_image] =>[orig_patent_app_number] => 10364720
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/364720 | System and method for low area self-timing in memory devices | Feb 9, 2003 | Issued |
Array
(
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[patent_doc_number] => 20030161250
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[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Memory device having reduced layout area'
[patent_app_type] => new
[patent_app_number] => 10/361322
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/361322 | Memory device having reduced layout area | Feb 9, 2003 | Issued |
Array
(
[id] => 7626087
[patent_doc_number] => 06768679
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-27
[patent_title] => 'Selection circuit for accurate memory read operations'
[patent_app_type] => B1
[patent_app_number] => 10/361378
[patent_app_country] => US
[patent_app_date] => 2003-02-10
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Array
(
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[patent_doc_number] => 20040037140
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-26
[patent_title] => 'Sense amplifier drive circuits responsive to predecoded column addresses and methods for operating the same'
[patent_app_type] => new
[patent_app_number] => 10/361320
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[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10361320
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/361320 | Sense amplifier drive circuits responsive to predecoded column addresses and methods for operating the same | Feb 9, 2003 | Issued |
Array
(
[id] => 7610499
[patent_doc_number] => 06842359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-11
[patent_title] => 'Content addressable memory device having an operation mode setting means'
[patent_app_type] => utility
[patent_app_number] => 10/360924
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[patent_app_date] => 2003-02-10
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/360924 | Content addressable memory device having an operation mode setting means | Feb 9, 2003 | Issued |
Array
(
[id] => 1122873
[patent_doc_number] => 06798697
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-28
[patent_title] => 'Non-volatile semiconductor memory device'
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[firstpage_image] =>[orig_patent_app_number] => 10360586
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/360586 | Non-volatile semiconductor memory device | Feb 5, 2003 | Issued |
Array
(
[id] => 1131006
[patent_doc_number] => 06791889
[patent_country] => US
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[patent_issue_date] => 2004-09-14
[patent_title] => 'Double data rate memory interface'
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[patent_app_number] => 10/358452
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[pdf_file] => patents/06/791/06791889.pdf
[firstpage_image] =>[orig_patent_app_number] => 10358452
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/358452 | Double data rate memory interface | Feb 3, 2003 | Issued |
Array
(
[id] => 1191110
[patent_doc_number] => 06735114
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-11
[patent_title] => 'Method of improving dynamic reference tracking for flash memory unit'
[patent_app_type] => B1
[patent_app_number] => 10/357879
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[pdf_file] => patents/06/735/06735114.pdf
[firstpage_image] =>[orig_patent_app_number] => 10357879
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/357879 | Method of improving dynamic reference tracking for flash memory unit | Feb 3, 2003 | Issued |
Array
(
[id] => 6828562
[patent_doc_number] => 20030179620
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/356482 | Semiconductor memory device | Feb 2, 2003 | Issued |
Array
(
[id] => 1158370
[patent_doc_number] => 06771545
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[patent_issue_date] => 2004-08-03
[patent_title] => 'Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array'
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[patent_app_number] => 10/353558
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[pdf_file] => patents/06/771/06771545.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/353558 | Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array | Jan 28, 2003 | Issued |
Array
(
[id] => 1074610
[patent_doc_number] => 06839278
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[patent_title] => 'Highly-integrated flash memory and mask ROM array architecture'
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Array
(
[id] => 7352380
[patent_doc_number] => 20040012998
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[patent_title] => 'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'
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Array
(
[id] => 7433878
[patent_doc_number] => 20040008546
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[patent_title] => 'Circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line'
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Array
(
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[patent_title] => 'Differential flash memory programming technique'
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Array
(
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[patent_title] => 'NONVOLATILE MEMORY INTEGRATED CIRCUIT HAVING VOLATILE UTILITY AND BUFFER MEMORIES, AND METHOD OF OPERATION THEREOF'
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Array
(
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/339458 | Method and circuit for repairing nonvolatile ferroelectric memory device | Jan 9, 2003 | Issued |
Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340342 | Method and apparatus for emulating an electrically erasable programmable read only memory (EEPROM) using non-volatile floating gate memory cells | Jan 9, 2003 | Issued |