
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1208621
[patent_doc_number] => 06717842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-06
[patent_title] => 'Static type semiconductor memory device with dummy memory cell'
[patent_app_type] => B2
[patent_app_number] => 10/339324
[patent_app_country] => US
[patent_app_date] => 2003-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 35
[patent_no_of_words] => 7739
[patent_no_of_claims] => 9
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/717/06717842.pdf
[firstpage_image] =>[orig_patent_app_number] => 10339324
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/339324 | Static type semiconductor memory device with dummy memory cell | Jan 9, 2003 | Issued |
Array
(
[id] => 1164460
[patent_doc_number] => 06762966
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-13
[patent_title] => 'Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor'
[patent_app_type] => B1
[patent_app_number] => 10/338928
[patent_app_country] => US
[patent_app_date] => 2003-01-08
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10338928
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338928 | Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor | Jan 7, 2003 | Issued |
Array
(
[id] => 6855079
[patent_doc_number] => 20030128580
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[patent_kind] => A1
[patent_issue_date] => 2003-07-10
[patent_title] => 'High-density magnetic random access memory device and method of operating the same'
[patent_app_type] => new
[patent_app_number] => 10/337262
[patent_app_country] => US
[patent_app_date] => 2003-01-07
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[firstpage_image] =>[orig_patent_app_number] => 10337262
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/337262 | High-density magnetic random access memory device and method of operating the same | Jan 6, 2003 | Abandoned |
Array
(
[id] => 6800291
[patent_doc_number] => 20030095455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/337322
[patent_app_country] => US
[patent_app_date] => 2003-01-07
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10337322
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/337322 | Semiconductor integrated circuit | Jan 6, 2003 | Issued |
Array
(
[id] => 6657385
[patent_doc_number] => 20030133346
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[patent_kind] => A1
[patent_issue_date] => 2003-07-17
[patent_title] => 'Semiconductor memory device'
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[patent_app_number] => 10/337375
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[firstpage_image] =>[orig_patent_app_number] => 10337375
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/337375 | Semiconductor memory device | Jan 6, 2003 | Issued |
Array
(
[id] => 1194876
[patent_doc_number] => 06731534
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-04
[patent_title] => 'Bit line tracking scheme with cell current variation and substrate noise consideration for SRAM devices'
[patent_app_type] => B1
[patent_app_number] => 10/338122
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[pdf_file] => patents/06/731/06731534.pdf
[firstpage_image] =>[orig_patent_app_number] => 10338122
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338122 | Bit line tracking scheme with cell current variation and substrate noise consideration for SRAM devices | Jan 6, 2003 | Issued |
Array
(
[id] => 1130912
[patent_doc_number] => 06791864
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-14
[patent_title] => 'Column voltage control for write'
[patent_app_type] => B2
[patent_app_number] => 10/337055
[patent_app_country] => US
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[pdf_file] => patents/06/791/06791864.pdf
[firstpage_image] =>[orig_patent_app_number] => 10337055
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/337055 | Column voltage control for write | Jan 5, 2003 | Issued |
Array
(
[id] => 7628765
[patent_doc_number] => 06819594
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-16
[patent_title] => 'Electrically erasable programmable logic device'
[patent_app_type] => B2
[patent_app_number] => 10/248282
[patent_app_country] => US
[patent_app_date] => 2003-01-06
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[pdf_file] => patents/06/819/06819594.pdf
[firstpage_image] =>[orig_patent_app_number] => 10248282
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/248282 | Electrically erasable programmable logic device | Jan 5, 2003 | Issued |
Array
(
[id] => 6855107
[patent_doc_number] => 20030128608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-10
[patent_title] => 'Sense amplifier driver circuits configured to track changes in memory cell pass transistor characteristics'
[patent_app_type] => new
[patent_app_number] => 10/336524
[patent_app_country] => US
[patent_app_date] => 2003-01-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/336524 | Sense amplifier driver circuits configured to track changes in memory cell pass transistor characteristics | Jan 2, 2003 | Issued |
Array
(
[id] => 1219911
[patent_doc_number] => 06707703
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-16
[patent_title] => 'Negative voltage generating circuit'
[patent_app_type] => B2
[patent_app_number] => 10/335921
[patent_app_country] => US
[patent_app_date] => 2003-01-03
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[pdf_file] => patents/06/707/06707703.pdf
[firstpage_image] =>[orig_patent_app_number] => 10335921
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/335921 | Negative voltage generating circuit | Jan 2, 2003 | Issued |
Array
(
[id] => 1145440
[patent_doc_number] => 06781912
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'Providing protection against transistor junction breakdowns from supply voltage'
[patent_app_type] => B2
[patent_app_number] => 10/335824
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[pdf_file] => patents/06/781/06781912.pdf
[firstpage_image] =>[orig_patent_app_number] => 10335824
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/335824 | Providing protection against transistor junction breakdowns from supply voltage | Dec 30, 2002 | Issued |
Array
(
[id] => 7374580
[patent_doc_number] => 20040027850
[patent_country] => US
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[patent_title] => 'Nonvolatile ferroelectric memory device with split word lines'
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Array
(
[id] => 6841943
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Array
(
[id] => 7297855
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Array
(
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Array
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Array
(
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Array
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