Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1208621 [patent_doc_number] => 06717842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Static type semiconductor memory device with dummy memory cell' [patent_app_type] => B2 [patent_app_number] => 10/339324 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 7739 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717842.pdf [firstpage_image] =>[orig_patent_app_number] => 10339324 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339324
Static type semiconductor memory device with dummy memory cell Jan 9, 2003 Issued
Array ( [id] => 1164460 [patent_doc_number] => 06762966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor' [patent_app_type] => B1 [patent_app_number] => 10/338928 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 5869 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762966.pdf [firstpage_image] =>[orig_patent_app_number] => 10338928 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338928
Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor Jan 7, 2003 Issued
Array ( [id] => 6855079 [patent_doc_number] => 20030128580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'High-density magnetic random access memory device and method of operating the same' [patent_app_type] => new [patent_app_number] => 10/337262 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3005 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128580.pdf [firstpage_image] =>[orig_patent_app_number] => 10337262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337262
High-density magnetic random access memory device and method of operating the same Jan 6, 2003 Abandoned
Array ( [id] => 6800291 [patent_doc_number] => 20030095455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/337322 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13520 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20030095455.pdf [firstpage_image] =>[orig_patent_app_number] => 10337322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337322
Semiconductor integrated circuit Jan 6, 2003 Issued
Array ( [id] => 6657385 [patent_doc_number] => 20030133346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/337375 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6110 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20030133346.pdf [firstpage_image] =>[orig_patent_app_number] => 10337375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337375
Semiconductor memory device Jan 6, 2003 Issued
Array ( [id] => 1194876 [patent_doc_number] => 06731534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Bit line tracking scheme with cell current variation and substrate noise consideration for SRAM devices' [patent_app_type] => B1 [patent_app_number] => 10/338122 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2179 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/731/06731534.pdf [firstpage_image] =>[orig_patent_app_number] => 10338122 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338122
Bit line tracking scheme with cell current variation and substrate noise consideration for SRAM devices Jan 6, 2003 Issued
Array ( [id] => 1130912 [patent_doc_number] => 06791864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Column voltage control for write' [patent_app_type] => B2 [patent_app_number] => 10/337055 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1763 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791864.pdf [firstpage_image] =>[orig_patent_app_number] => 10337055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337055
Column voltage control for write Jan 5, 2003 Issued
Array ( [id] => 7628765 [patent_doc_number] => 06819594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Electrically erasable programmable logic device' [patent_app_type] => B2 [patent_app_number] => 10/248282 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4493 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819594.pdf [firstpage_image] =>[orig_patent_app_number] => 10248282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248282
Electrically erasable programmable logic device Jan 5, 2003 Issued
Array ( [id] => 6855107 [patent_doc_number] => 20030128608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Sense amplifier driver circuits configured to track changes in memory cell pass transistor characteristics' [patent_app_type] => new [patent_app_number] => 10/336524 [patent_app_country] => US [patent_app_date] => 2003-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4358 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128608.pdf [firstpage_image] =>[orig_patent_app_number] => 10336524 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336524
Sense amplifier driver circuits configured to track changes in memory cell pass transistor characteristics Jan 2, 2003 Issued
Array ( [id] => 1219911 [patent_doc_number] => 06707703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Negative voltage generating circuit' [patent_app_type] => B2 [patent_app_number] => 10/335921 [patent_app_country] => US [patent_app_date] => 2003-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4401 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707703.pdf [firstpage_image] =>[orig_patent_app_number] => 10335921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/335921
Negative voltage generating circuit Jan 2, 2003 Issued
Array ( [id] => 1145440 [patent_doc_number] => 06781912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Providing protection against transistor junction breakdowns from supply voltage' [patent_app_type] => B2 [patent_app_number] => 10/335824 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5876 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781912.pdf [firstpage_image] =>[orig_patent_app_number] => 10335824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/335824
Providing protection against transistor junction breakdowns from supply voltage Dec 30, 2002 Issued
Array ( [id] => 7374580 [patent_doc_number] => 20040027850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Nonvolatile ferroelectric memory device with split word lines' [patent_app_type] => new [patent_app_number] => 10/331458 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14812 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027850.pdf [firstpage_image] =>[orig_patent_app_number] => 10331458 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331458
Nonvolatile ferroelectric memory device with split word lines Dec 30, 2002 Issued
Array ( [id] => 6841943 [patent_doc_number] => 20030147290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Power supply circuit structure for a row decoder of a multilevel non-volatile memory device' [patent_app_type] => new [patent_app_number] => 10/334126 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3988 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20030147290.pdf [firstpage_image] =>[orig_patent_app_number] => 10334126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/334126
Power supply circuit structure for a row decoder of a multilevel non-volatile memory device Dec 29, 2002 Issued
Array ( [id] => 7297855 [patent_doc_number] => 20040125677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Stable memory cell read' [patent_app_type] => new [patent_app_number] => 10/334456 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2387 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20040125677.pdf [firstpage_image] =>[orig_patent_app_number] => 10334456 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/334456
Stable memory cell read Dec 29, 2002 Issued
Array ( [id] => 1099302 [patent_doc_number] => 06822910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Non-volatile memory and operating method thereof' [patent_app_type] => B2 [patent_app_number] => 10/248220 [patent_app_country] => US [patent_app_date] => 2002-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4108 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822910.pdf [firstpage_image] =>[orig_patent_app_number] => 10248220 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248220
Non-volatile memory and operating method thereof Dec 28, 2002 Issued
Array ( [id] => 1131001 [patent_doc_number] => 06791888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Semiconductor memory device having preamble function' [patent_app_type] => B2 [patent_app_number] => 10/329826 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5703 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791888.pdf [firstpage_image] =>[orig_patent_app_number] => 10329826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329826
Semiconductor memory device having preamble function Dec 26, 2002 Issued
Array ( [id] => 1108180 [patent_doc_number] => 06813197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'DLL driving circuit for use in semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/329564 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3641 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813197.pdf [firstpage_image] =>[orig_patent_app_number] => 10329564 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329564
DLL driving circuit for use in semiconductor memory device Dec 26, 2002 Issued
Array ( [id] => 1156008 [patent_doc_number] => 06775180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Low power state retention' [patent_app_type] => B2 [patent_app_number] => 10/329124 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4180 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775180.pdf [firstpage_image] =>[orig_patent_app_number] => 10329124 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329124
Low power state retention Dec 22, 2002 Issued
Array ( [id] => 1219952 [patent_doc_number] => 06707716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/323921 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 0 [patent_no_of_words] => 7648 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707716.pdf [firstpage_image] =>[orig_patent_app_number] => 10323921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/323921
Non-volatile semiconductor memory device Dec 19, 2002 Issued
Array ( [id] => 6739088 [patent_doc_number] => 20030156457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Memory device trapping charges in insulating film to store information in non-volatile manner' [patent_app_type] => new [patent_app_number] => 10/319520 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20030156457.pdf [firstpage_image] =>[orig_patent_app_number] => 10319520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/319520
Memory device trapping charges in insulating film to store information in non-volatile manner Dec 15, 2002 Issued
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