Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1191161 [patent_doc_number] => 06735143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'System for reducing power consumption in memory devices' [patent_app_type] => B2 [patent_app_number] => 10/320222 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3880 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735143.pdf [firstpage_image] =>[orig_patent_app_number] => 10320222 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/320222
System for reducing power consumption in memory devices Dec 15, 2002 Issued
Array ( [id] => 6682003 [patent_doc_number] => 20030117867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/318020 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5218 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117867.pdf [firstpage_image] =>[orig_patent_app_number] => 10318020 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318020
Semiconductor memory device Dec 12, 2002 Issued
Array ( [id] => 1219941 [patent_doc_number] => 06707710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Magnetic memory device with larger reference cell' [patent_app_type] => B1 [patent_app_number] => 10/318520 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6200 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707710.pdf [firstpage_image] =>[orig_patent_app_number] => 10318520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318520
Magnetic memory device with larger reference cell Dec 11, 2002 Issued
Array ( [id] => 1070134 [patent_doc_number] => 06845024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-18 [patent_title] => 'Result compare circuit and method for content addressable memory (CAM) device' [patent_app_type] => utility [patent_app_number] => 10/317918 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 9339 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/845/06845024.pdf [firstpage_image] =>[orig_patent_app_number] => 10317918 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/317918
Result compare circuit and method for content addressable memory (CAM) device Dec 11, 2002 Issued
Array ( [id] => 1220113 [patent_doc_number] => 06707755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'High voltage driver' [patent_app_type] => B1 [patent_app_number] => 10/316728 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4052 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707755.pdf [firstpage_image] =>[orig_patent_app_number] => 10316728 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316728
High voltage driver Dec 10, 2002 Issued
Array ( [id] => 7346602 [patent_doc_number] => 20040047177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Magnetic random access memory' [patent_app_type] => new [patent_app_number] => 10/310022 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10590 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20040047177.pdf [firstpage_image] =>[orig_patent_app_number] => 10310022 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310022
Magnetic random access memory Dec 4, 2002 Issued
Array ( [id] => 1199361 [patent_doc_number] => 06728155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Serial access memory and data write/read method' [patent_app_type] => B2 [patent_app_number] => 10/307399 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17633 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728155.pdf [firstpage_image] =>[orig_patent_app_number] => 10307399 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/307399
Serial access memory and data write/read method Dec 1, 2002 Issued
Array ( [id] => 1172604 [patent_doc_number] => 06760240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'CAM cell with interdigitated search and bit lines' [patent_app_type] => B2 [patent_app_number] => 10/065822 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1549 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760240.pdf [firstpage_image] =>[orig_patent_app_number] => 10065822 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065822
CAM cell with interdigitated search and bit lines Nov 21, 2002 Issued
Array ( [id] => 1216161 [patent_doc_number] => 06711082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method and implementation of an on-chip self refresh feature' [patent_app_type] => B1 [patent_app_number] => 10/299026 [patent_app_country] => US [patent_app_date] => 2002-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4961 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711082.pdf [firstpage_image] =>[orig_patent_app_number] => 10299026 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299026
Method and implementation of an on-chip self refresh feature Nov 17, 2002 Issued
Array ( [id] => 7624519 [patent_doc_number] => 06724657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Semiconductor device with improved latch arrangement' [patent_app_type] => B2 [patent_app_number] => 10/290492 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 13163 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724657.pdf [firstpage_image] =>[orig_patent_app_number] => 10290492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290492
Semiconductor device with improved latch arrangement Nov 7, 2002 Issued
Array ( [id] => 7358206 [patent_doc_number] => 20040090818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Design concept for SRAM read margin' [patent_app_type] => new [patent_app_number] => 10/290622 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3776 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090818.pdf [firstpage_image] =>[orig_patent_app_number] => 10290622 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290622
Design concept for SRAM read margin Nov 7, 2002 Issued
Array ( [id] => 1180195 [patent_doc_number] => 06751125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Gate voltage reduction in a memory read' [patent_app_type] => B2 [patent_app_number] => 10/287328 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3713 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751125.pdf [firstpage_image] =>[orig_patent_app_number] => 10287328 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287328
Gate voltage reduction in a memory read Nov 3, 2002 Issued
Array ( [id] => 6673111 [patent_doc_number] => 20030058714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Modular memory structure having adaptable redundancy circuitry' [patent_app_type] => new [patent_app_number] => 10/286889 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1670 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20030058714.pdf [firstpage_image] =>[orig_patent_app_number] => 10286889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/286889
Modular memory structure having adaptable redundancy circuitry Nov 3, 2002 Issued
Array ( [id] => 1191165 [patent_doc_number] => 06735145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method and circuit for optimizing power consumption and performance of driver circuits' [patent_app_type] => B1 [patent_app_number] => 10/065626 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3725 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735145.pdf [firstpage_image] =>[orig_patent_app_number] => 10065626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065626
Method and circuit for optimizing power consumption and performance of driver circuits Nov 3, 2002 Issued
Array ( [id] => 1227309 [patent_doc_number] => 06700814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Sense amplifier bias circuit for a memory having at least two distinct resistance states' [patent_app_type] => B1 [patent_app_number] => 10/283622 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7509 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700814.pdf [firstpage_image] =>[orig_patent_app_number] => 10283622 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283622
Sense amplifier bias circuit for a memory having at least two distinct resistance states Oct 29, 2002 Issued
Array ( [id] => 7434013 [patent_doc_number] => 20040008566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'LATENCY CONTROL CIRCUIT AND METHOD OF LATENCY CONTROL' [patent_app_type] => new [patent_app_number] => 10/283124 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5415 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20040008566.pdf [firstpage_image] =>[orig_patent_app_number] => 10283124 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283124
Latency control circuit and method of latency control Oct 29, 2002 Issued
Array ( [id] => 1275838 [patent_doc_number] => 06654293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Methods and apparatus for reading memory device register data' [patent_app_type] => B2 [patent_app_number] => 10/283657 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6302 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654293.pdf [firstpage_image] =>[orig_patent_app_number] => 10283657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283657
Methods and apparatus for reading memory device register data Oct 28, 2002 Issued
Array ( [id] => 1223550 [patent_doc_number] => 06704242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B2 [patent_app_number] => 10/279920 [patent_app_country] => US [patent_app_date] => 2002-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9413 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704242.pdf [firstpage_image] =>[orig_patent_app_number] => 10279920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279920
Semiconductor integrated circuit Oct 24, 2002 Issued
Array ( [id] => 1212488 [patent_doc_number] => 06714454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell' [patent_app_type] => B2 [patent_app_number] => 10/280722 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714454.pdf [firstpage_image] =>[orig_patent_app_number] => 10280722 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/280722
Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell Oct 23, 2002 Issued
Array ( [id] => 1216192 [patent_doc_number] => 06711092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Semiconductor memory with multiple timing loops' [patent_app_type] => B1 [patent_app_number] => 10/279428 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4148 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711092.pdf [firstpage_image] =>[orig_patent_app_number] => 10279428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279428
Semiconductor memory with multiple timing loops Oct 23, 2002 Issued
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