Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1145240 [patent_doc_number] => 06781877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells' [patent_app_type] => B2 [patent_app_number] => 10/237426 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5884 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781877.pdf [firstpage_image] =>[orig_patent_app_number] => 10237426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/237426
Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells Sep 5, 2002 Issued
Array ( [id] => 944824 [patent_doc_number] => 06967880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Semiconductor memory test device' [patent_app_type] => utility [patent_app_number] => 10/236313 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3550 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967880.pdf [firstpage_image] =>[orig_patent_app_number] => 10236313 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/236313
Semiconductor memory test device Sep 5, 2002 Issued
Array ( [id] => 6719048 [patent_doc_number] => 20030052735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Ferroelectric memory device and a method for driving the same' [patent_app_type] => new [patent_app_number] => 10/233429 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6102 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20030052735.pdf [firstpage_image] =>[orig_patent_app_number] => 10233429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233429
Ferroelectric memory device and a method for driving the same Sep 3, 2002 Issued
Array ( [id] => 6754605 [patent_doc_number] => 20030002381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Semiconductor memory for logic-hybrid memory' [patent_app_type] => new [patent_app_number] => 10/232531 [patent_app_country] => US [patent_app_date] => 2002-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4070 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002381.pdf [firstpage_image] =>[orig_patent_app_number] => 10232531 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232531
Semiconductor memory for logic-hybrid memory Sep 2, 2002 Issued
Array ( [id] => 1114778 [patent_doc_number] => 06804133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Selective match line control circuit for content addressable memory array' [patent_app_type] => B1 [patent_app_number] => 10/233022 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3102 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804133.pdf [firstpage_image] =>[orig_patent_app_number] => 10233022 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233022
Selective match line control circuit for content addressable memory array Aug 29, 2002 Issued
Array ( [id] => 7131874 [patent_doc_number] => 20040042304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage' [patent_app_type] => new [patent_app_number] => 10/231626 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6246 [patent_no_of_claims] => 93 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042304.pdf [firstpage_image] =>[orig_patent_app_number] => 10231626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231626
Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage Aug 28, 2002 Issued
Array ( [id] => 6782053 [patent_doc_number] => 20030063500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Flash memory sector tagging for consecutive sector erase or bank erase' [patent_app_type] => new [patent_app_number] => 10/229921 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5522 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20030063500.pdf [firstpage_image] =>[orig_patent_app_number] => 10229921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229921
Flash memory sector tagging for consecutive sector erase or bank erase Aug 27, 2002 Issued
Array ( [id] => 6777573 [patent_doc_number] => 20030048654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Ferroelectric random access memory configurable output driver circuit' [patent_app_type] => new [patent_app_number] => 10/233276 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2746 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20030048654.pdf [firstpage_image] =>[orig_patent_app_number] => 10233276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233276
Ferroelectric random access memory configurable output driver circuit Aug 27, 2002 Issued
Array ( [id] => 6719660 [patent_doc_number] => 20030053348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Flash memory array architecture' [patent_app_type] => new [patent_app_number] => 10/228824 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4122 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053348.pdf [firstpage_image] =>[orig_patent_app_number] => 10228824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228824
Flash memory array architecture Aug 26, 2002 Issued
Array ( [id] => 1227330 [patent_doc_number] => 06700827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Cam circuit with error correction' [patent_app_type] => B2 [patent_app_number] => 10/226512 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 11618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700827.pdf [firstpage_image] =>[orig_patent_app_number] => 10226512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226512
Cam circuit with error correction Aug 22, 2002 Issued
Array ( [id] => 7386360 [patent_doc_number] => 20040037157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Synchronous memory with open page' [patent_app_type] => new [patent_app_number] => 10/225324 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037157.pdf [firstpage_image] =>[orig_patent_app_number] => 10225324 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225324
Synchronous memory with open page Aug 20, 2002 Issued
Array ( [id] => 6833659 [patent_doc_number] => 20030161204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Semiconductor memory device capable of performing burn-in test at high speed' [patent_app_type] => new [patent_app_number] => 10/223326 [patent_app_country] => US [patent_app_date] => 2002-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 23240 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20030161204.pdf [firstpage_image] =>[orig_patent_app_number] => 10223326 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/223326
Semiconductor memory device capable of performing burn-in test at high speed Aug 19, 2002 Issued
Array ( [id] => 1220043 [patent_doc_number] => 06707732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Method of quickly determining work line failure type' [patent_app_type] => B2 [patent_app_number] => 10/222320 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2064 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707732.pdf [firstpage_image] =>[orig_patent_app_number] => 10222320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222320
Method of quickly determining work line failure type Aug 15, 2002 Issued
Array ( [id] => 6705212 [patent_doc_number] => 20030151946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Nonvolatile semiconductor memory device having control circuit' [patent_app_type] => new [patent_app_number] => 10/216729 [patent_app_country] => US [patent_app_date] => 2002-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 16491 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20030151946.pdf [firstpage_image] =>[orig_patent_app_number] => 10216729 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/216729
Nonvolatile semiconductor memory device having control circuit Aug 12, 2002 Issued
Array ( [id] => 639772 [patent_doc_number] => 07126866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Low power ROM architecture' [patent_app_type] => utility [patent_app_number] => 10/215699 [patent_app_country] => US [patent_app_date] => 2002-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2443 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126866.pdf [firstpage_image] =>[orig_patent_app_number] => 10215699 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215699
Low power ROM architecture Aug 9, 2002 Issued
Array ( [id] => 1219961 [patent_doc_number] => 06707717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Current sense amplifier with dynamic pre-charge' [patent_app_type] => B2 [patent_app_number] => 10/214120 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2375 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707717.pdf [firstpage_image] =>[orig_patent_app_number] => 10214120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214120
Current sense amplifier with dynamic pre-charge Aug 7, 2002 Issued
Array ( [id] => 6673112 [patent_doc_number] => 20030058715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Nonvolatile semiconductor memory device and method for testing the same' [patent_app_type] => new [patent_app_number] => 10/208829 [patent_app_country] => US [patent_app_date] => 2002-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5633 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20030058715.pdf [firstpage_image] =>[orig_patent_app_number] => 10208829 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/208829
Nonvolatile semiconductor memory device and method for testing the same Jul 31, 2002 Issued
Array ( [id] => 6714811 [patent_doc_number] => 20030026159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Fuse programmable I/O organization' [patent_app_type] => new [patent_app_number] => 10/210628 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4641 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20030026159.pdf [firstpage_image] =>[orig_patent_app_number] => 10210628 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210628
Fuse programmable I/O organization Jul 30, 2002 Issued
Array ( [id] => 1212484 [patent_doc_number] => 06714452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Non-volatile semiconductor memory device and semiconductor disk device' [patent_app_type] => B2 [patent_app_number] => 10/205426 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 9260 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714452.pdf [firstpage_image] =>[orig_patent_app_number] => 10205426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205426
Non-volatile semiconductor memory device and semiconductor disk device Jul 25, 2002 Issued
Array ( [id] => 1208730 [patent_doc_number] => 06717884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Synchronous memory device with reduced address pins' [patent_app_type] => B2 [patent_app_number] => 10/198926 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2039 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717884.pdf [firstpage_image] =>[orig_patent_app_number] => 10198926 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/198926
Synchronous memory device with reduced address pins Jul 21, 2002 Issued
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