Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18639250 [patent_doc_number] => 11763866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => SRAM with scan mode [patent_app_type] => utility [patent_app_number] => 17/702770 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8766 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/702770
SRAM with scan mode Mar 22, 2022 Issued
Array ( [id] => 19062912 [patent_doc_number] => 11942157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Variable bit line bias for nonvolatile memory [patent_app_type] => utility [patent_app_number] => 17/697252 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697252
Variable bit line bias for nonvolatile memory Mar 16, 2022 Issued
Array ( [id] => 18967204 [patent_doc_number] => 11900982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/695263 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10751 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695263
Semiconductor device Mar 14, 2022 Issued
Array ( [id] => 18488128 [patent_doc_number] => 20230215476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/695613 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695613 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695613
Semiconductor device related to operation of internal circuits Mar 14, 2022 Issued
Array ( [id] => 17708225 [patent_doc_number] => 20220208233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY PACKAGE HAVING STACKED ARRAY DIES AND REDUCED DRIVER LOAD [patent_app_type] => utility [patent_app_number] => 17/694649 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694649
Memory package having stacked array dies and reduced driver load Mar 13, 2022 Issued
Array ( [id] => 18918982 [patent_doc_number] => 11881270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Detection circuit, semiconductor memory device, memory system [patent_app_type] => utility [patent_app_number] => 17/693948 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7616 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693948
Detection circuit, semiconductor memory device, memory system Mar 13, 2022 Issued
Array ( [id] => 18631484 [patent_doc_number] => 20230290386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => APPARATUSES AND METHODS OF POWER SUPPLY CONTROL FOR SENSE AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 17/692066 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692066
Apparatuses and methods of power supply control for sense amplifiers Mar 9, 2022 Issued
Array ( [id] => 18967202 [patent_doc_number] => 11900980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Techniques to mitigate asymmetric long delay stress [patent_app_type] => utility [patent_app_number] => 17/690614 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13970 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690614
Techniques to mitigate asymmetric long delay stress Mar 8, 2022 Issued
Array ( [id] => 18174953 [patent_doc_number] => 11574670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Memory device for reducing resources used for training [patent_app_type] => utility [patent_app_number] => 17/690137 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 21002 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690137
Memory device for reducing resources used for training Mar 8, 2022 Issued
Array ( [id] => 17900476 [patent_doc_number] => 20220310138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR DEVICE AND CONTINUOUS READING METHOD [patent_app_type] => utility [patent_app_number] => 17/688906 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/688906
Semiconductor device and continuous reading method Mar 7, 2022 Issued
Array ( [id] => 18243497 [patent_doc_number] => 20230075808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD DETERMINING TARGET STATUS READ CHECK PERIOD IN THERMAL THROTTLING MODE [patent_app_type] => utility [patent_app_number] => 17/686104 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686104 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/686104
Memory system and operating method determining target status read check period in thermal throttling mode Mar 2, 2022 Issued
Array ( [id] => 18585724 [patent_doc_number] => 20230267988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => APPARATUS, METHOD AND SYSTEM TO REDUCE MEMORY WINDOW LATENCY AND READ DISTURB IN A MEMORY DEVICE FOR MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/679971 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679971
Apparatus, method and system to reduce memory window latency and read disturb in a memory device for memory operations Feb 23, 2022 Issued
Array ( [id] => 18124923 [patent_doc_number] => 20230010537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => METHOD OF DIFFERENTIATED THERMAL THROTTLING OF MEMORY AND SYSTEM THEREFOR [patent_app_type] => utility [patent_app_number] => 17/680044 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680044 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680044
Method of differentiated thermal throttling of memory and system therefor Feb 23, 2022 Issued
Array ( [id] => 18950754 [patent_doc_number] => 11894056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Non-volatile memory with efficient word line hook-up [patent_app_type] => utility [patent_app_number] => 17/677907 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 36 [patent_no_of_words] => 20897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17677907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/677907
Non-volatile memory with efficient word line hook-up Feb 21, 2022 Issued
Array ( [id] => 18669675 [patent_doc_number] => 11776585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory device including a pass transistor circuit and a discharge transistor circuit [patent_app_type] => utility [patent_app_number] => 17/674829 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7978 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674829
Memory device including a pass transistor circuit and a discharge transistor circuit Feb 16, 2022 Issued
Array ( [id] => 19153581 [patent_doc_number] => 11978502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Input sampling method, input sampling circuit and semiconductor memory [patent_app_type] => utility [patent_app_number] => 17/651421 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6752 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651421 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/651421
Input sampling method, input sampling circuit and semiconductor memory Feb 15, 2022 Issued
Array ( [id] => 18570237 [patent_doc_number] => 20230260574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SELF-REFERENCED AND REGULATED SENSING SOLUTION FOR PHASE CHANGE MEMORY WITH OVONIC THRESHOLD SWITCH [patent_app_type] => utility [patent_app_number] => 17/673550 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673550
Self-referenced and regulated sensing solution for phase change memory with ovonic threshold switch Feb 15, 2022 Issued
Array ( [id] => 18570245 [patent_doc_number] => 20230260582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE [patent_app_type] => utility [patent_app_number] => 17/673172 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673172
Non-volatile memory with efficient testing during erase Feb 15, 2022 Issued
Array ( [id] => 17833351 [patent_doc_number] => 20220270655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => MEMORY CONTROL CIRCUIT AND METHOD FOR CONTROLLING THE SAME [patent_app_type] => utility [patent_app_number] => 17/668415 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668415
Memory control circuit and method for controlling the same Feb 9, 2022 Issued
Array ( [id] => 18751294 [patent_doc_number] => 11810612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Apparatuses and methods for row hammer based cache lockdown [patent_app_type] => utility [patent_app_number] => 17/591319 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9745 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591319
Apparatuses and methods for row hammer based cache lockdown Feb 1, 2022 Issued
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