Search

Huan Hoang

Examiner (ID: 18810, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2154, 2827, 2511
Total Applications
3293
Issued Applications
3069
Pending Applications
116
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17932951 [patent_doc_number] => 20220328077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL [patent_app_type] => utility [patent_app_number] => 17/852659 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/852659
Header layout design including backside power rail Jun 28, 2022 Issued
Array ( [id] => 19639494 [patent_doc_number] => 12170107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Self-refresh state with decreased power consumption [patent_app_type] => utility [patent_app_number] => 17/808818 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17808818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/808818
Self-refresh state with decreased power consumption Jun 23, 2022 Issued
Array ( [id] => 18514374 [patent_doc_number] => 20230230629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => METHOD AND DEVICE FOR TESTING MEMORY AND METHOD FOR SIMULATED TESTING [patent_app_type] => utility [patent_app_number] => 17/808297 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17808297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/808297
Method and device for testing memory and method for simulated testing Jun 21, 2022 Issued
Array ( [id] => 19108474 [patent_doc_number] => 11961587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Clock driver and memory device comprising the same [patent_app_type] => utility [patent_app_number] => 17/847156 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4651 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/847156
Clock driver and memory device comprising the same Jun 21, 2022 Issued
Array ( [id] => 17917171 [patent_doc_number] => 20220319567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => FFT-DRAM [patent_app_type] => utility [patent_app_number] => 17/846985 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846985
FFT-DRAM Jun 21, 2022 Issued
Array ( [id] => 19679061 [patent_doc_number] => 12190932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory device, memory controller, and methods thereof [patent_app_type] => utility [patent_app_number] => 17/806673 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 46 [patent_no_of_words] => 17213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806673
Memory device, memory controller, and methods thereof Jun 12, 2022 Issued
Array ( [id] => 19375724 [patent_doc_number] => 12067294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Interface circuit for converting a serial data stream to a parallel data scheme with data strobe preamble information in the serial data stream [patent_app_type] => utility [patent_app_number] => 17/833657 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833657
Interface circuit for converting a serial data stream to a parallel data scheme with data strobe preamble information in the serial data stream Jun 5, 2022 Issued
Array ( [id] => 18299736 [patent_doc_number] => 20230109422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => MEMORY CONTROLLER AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/831284 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831284
Memory controller and storage device Jun 1, 2022 Issued
Array ( [id] => 18820760 [patent_doc_number] => 20230395101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MULTI-LEVEL CELLS, AND RELATED ARRAYS, DEVICES, SYSTEMS, AND METHODS [patent_app_type] => utility [patent_app_number] => 17/805090 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805090
Multi-level cells, and related arrays, devices, systems, and methods Jun 1, 2022 Issued
Array ( [id] => 19610787 [patent_doc_number] => 12159667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Internal reference resistor for non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/831414 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831414
Internal reference resistor for non-volatile memory Jun 1, 2022 Issued
Array ( [id] => 19123379 [patent_doc_number] => 11967373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Pre-decoder circuitry [patent_app_type] => utility [patent_app_number] => 17/831311 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831311 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831311
Pre-decoder circuitry Jun 1, 2022 Issued
Array ( [id] => 19552756 [patent_doc_number] => 12136467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Tracking the effects of voltage and temperature on a memory device using an internal oscillator [patent_app_type] => utility [patent_app_number] => 17/831114 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9378 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831114
Tracking the effects of voltage and temperature on a memory device using an internal oscillator Jun 1, 2022 Issued
Array ( [id] => 19213444 [patent_doc_number] => 12002516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Memory block characteristic determination [patent_app_type] => utility [patent_app_number] => 17/831350 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11851 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831350
Memory block characteristic determination Jun 1, 2022 Issued
Array ( [id] => 20820704 [patent_doc_number] => 12676177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-07 [patent_title] => Dynamic random access memory (DRAM) with configurable wordline and bitline voltages [patent_app_type] => utility [patent_app_number] => 18/566558 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18566558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/566558
Dynamic random access memory (DRAM) with configurable wordline and bitline voltages May 30, 2022 Issued
Array ( [id] => 19376443 [patent_doc_number] => 12068021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Low power clock injection during idle mode operations [patent_app_type] => utility [patent_app_number] => 17/746757 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4632 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746757
Low power clock injection during idle mode operations May 16, 2022 Issued
Array ( [id] => 19459950 [patent_doc_number] => 12100452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Non-volatile memory device [patent_app_type] => utility [patent_app_number] => 17/742879 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 15956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742879
Non-volatile memory device May 11, 2022 Issued
Array ( [id] => 19356733 [patent_doc_number] => 12057188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Use of data latches for plane level compression of soft bit data in non-volatile memories [patent_app_type] => utility [patent_app_number] => 17/742982 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 37 [patent_no_of_words] => 24932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742982
Use of data latches for plane level compression of soft bit data in non-volatile memories May 11, 2022 Issued
Array ( [id] => 18532994 [patent_doc_number] => 20230238069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => NON-VOLATILE MEMORY DEVICE INCLUDING SENSE AMPLIFIER AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/741635 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741635 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741635
Non-volatile memory device including sense amplifier and method for operating the same May 10, 2022 Issued
Array ( [id] => 19414504 [patent_doc_number] => 12080336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Apparatuses and methods for compensated sense amplifier with cross coupled N-type transistors [patent_app_type] => utility [patent_app_number] => 17/662198 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5653 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662198
Apparatuses and methods for compensated sense amplifier with cross coupled N-type transistors May 4, 2022 Issued
Array ( [id] => 18766768 [patent_doc_number] => 11817175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Enable signal generation circuit and semiconductor apparatus using the same [patent_app_type] => utility [patent_app_number] => 17/734893 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734893
Enable signal generation circuit and semiconductor apparatus using the same May 1, 2022 Issued
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