Huan Hoang

Array ( [id] => 1521897 [patent_doc_number] => 06502225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system' [patent_app_type] => B2 [patent_app_number] => 10/080740 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 44 [patent_no_of_words] => 14685 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502225.pdf [firstpage_image] =>[orig_patent_app_number] => 10080740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1303617 [patent_doc_number] => 06628536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/076426 [patent_app_country] => US [patent_app_date] => 2002-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4313 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/628/06628536.pdf [firstpage_image] =>[orig_patent_app_number] => 10076426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1406816 [patent_doc_number] => 06549457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Using multiple status bits per cell for handling power failures during write operations' [patent_app_type] => B1 [patent_app_number] => 10/077428 [patent_app_country] => US [patent_app_date] => 2002-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1417 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549457.pdf [firstpage_image] =>[orig_patent_app_number] => 10077428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429384 [patent_doc_number] => 06515910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM' [patent_app_type] => B1 [patent_app_number] => 10/076826 [patent_app_country] => US [patent_app_date] => 2002-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7211 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515910.pdf [firstpage_image] =>[orig_patent_app_number] => 10076826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6764735 [patent_doc_number] => 20030099133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Flash memory device' [patent_app_type] => new [patent_app_number] => 10/071226 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2005 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20030099133.pdf [firstpage_image] =>[orig_patent_app_number] => 10071226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1407074 [patent_doc_number] => 06549471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Adiabatic differential driver' [patent_app_type] => B1 [patent_app_number] => 10/073722 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2494 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549471.pdf [firstpage_image] =>[orig_patent_app_number] => 10073722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1395880 [patent_doc_number] => 06560133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Content addressable memory device with advanced precharge timing' [patent_app_type] => B2 [patent_app_number] => 10/066628 [patent_app_country] => US [patent_app_date] => 2002-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4252 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560133.pdf [firstpage_image] =>[orig_patent_app_number] => 10066628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6207219 [patent_doc_number] => 20020071305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Register file scheme' [patent_app_type] => new [patent_app_number] => 10/067491 [patent_app_country] => US [patent_app_date] => 2002-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5276 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20020071305.pdf [firstpage_image] =>[orig_patent_app_number] => 10067491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6754544 [patent_doc_number] => 20030002320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Memory device' [patent_app_type] => new [patent_app_number] => 10/060226 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6443 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002320.pdf [firstpage_image] =>[orig_patent_app_number] => 10060226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1310473 [patent_doc_number] => 06621728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method of writing a four-transistor memory cell array' [patent_app_type] => B2 [patent_app_number] => 10/061925 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10911 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621728.pdf [firstpage_image] =>[orig_patent_app_number] => 10061925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7630494 [patent_doc_number] => 06636442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Non-volatile memory element having a cascoded transistor scheme to reduce oxide field stress' [patent_app_type] => B2 [patent_app_number] => 10/059624 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1714 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636442.pdf [firstpage_image] =>[orig_patent_app_number] => 10059624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5827233 [patent_doc_number] => 20020067653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Semiconductor memory having an overlaid bus structure' [patent_app_type] => new [patent_app_number] => 10/057031 [patent_app_country] => US [patent_app_date] => 2002-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14234 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067653.pdf [firstpage_image] =>[orig_patent_app_number] => 10057031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1410303 [patent_doc_number] => 06545913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Memory cell of nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/052742 [patent_app_country] => US [patent_app_date] => 2002-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 14673 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545913.pdf [firstpage_image] =>[orig_patent_app_number] => 10052742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1350246 [patent_doc_number] => 06590826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Self-addressing FIFO' [patent_app_type] => B1 [patent_app_number] => 10/056320 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1890 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590826.pdf [firstpage_image] =>[orig_patent_app_number] => 10056320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6173025 [patent_doc_number] => 20020154535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'High density non-volatile memory device' [patent_app_type] => new [patent_app_number] => 10/053814 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 33567 [patent_no_of_claims] => 115 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20020154535.pdf [firstpage_image] =>[orig_patent_app_number] => 10053814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1064789 [patent_doc_number] => 06850441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Noise reduction technique for transistors and small devices utilizing an episodic agitation' [patent_app_type] => utility [patent_app_number] => 10/052924 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 14260 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/850/06850441.pdf [firstpage_image] =>[orig_patent_app_number] => 10052924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6423092 [patent_doc_number] => 20020126549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Embedded memory and method of arranging fuses thereof' [patent_app_type] => new [patent_app_number] => 10/051824 [patent_app_country] => US [patent_app_date] => 2002-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1995 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126549.pdf [firstpage_image] =>[orig_patent_app_number] => 10051824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5919848 [patent_doc_number] => 20020114198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Semiconductor storage device formed to optimize test technique and redundancy technology' [patent_app_type] => new [patent_app_number] => 10/053524 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 39940 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20020114198.pdf [firstpage_image] =>[orig_patent_app_number] => 10053524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6719677 [patent_doc_number] => 20030053365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Apparatus and method for inputting address signals in semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/046828 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1533 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053365.pdf [firstpage_image] =>[orig_patent_app_number] => 10046828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1359138 [patent_doc_number] => 06584021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Semiconductor memory having a delay locked loop' [patent_app_type] => B2 [patent_app_number] => 10/047824 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3524 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584021.pdf [firstpage_image] =>[orig_patent_app_number] => 10047824 [rel_patent_id] =>[rel_patent_doc_number] =>)