Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6303928 [patent_doc_number] => 20020093865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/043324 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3939 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093865.pdf [firstpage_image] =>[orig_patent_app_number] => 10043324 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043324
Semiconductor memory device Jan 13, 2002 Issued
Array ( [id] => 6695727 [patent_doc_number] => 20030107921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Method for operating a non-volatile memory' [patent_app_type] => new [patent_app_number] => 10/047720 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4017 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107921.pdf [firstpage_image] =>[orig_patent_app_number] => 10047720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/047720
Method for operating a non-volatile memory Jan 13, 2002 Abandoned
Array ( [id] => 7465126 [patent_doc_number] => 20040095808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Nonvolatile semiconductor storage device' [patent_app_type] => new [patent_app_number] => 10/250922 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 16065 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095808.pdf [firstpage_image] =>[orig_patent_app_number] => 10250922 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/250922
Nonvolatile semiconductor storage device Jan 10, 2002 Issued
Array ( [id] => 1359224 [patent_doc_number] => 06584028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Memory system and semiconductor memory device for enhancing bus efficiency and refresh method of the semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/044323 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3378 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584028.pdf [firstpage_image] =>[orig_patent_app_number] => 10044323 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044323
Memory system and semiconductor memory device for enhancing bus efficiency and refresh method of the semiconductor memory device Jan 9, 2002 Issued
Array ( [id] => 1325411 [patent_doc_number] => 06606262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Magnetoresistive random access memory (MRAM) with on-chip automatic determination of optimized write current method and apparatus' [patent_app_type] => B2 [patent_app_number] => 10/044724 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606262.pdf [firstpage_image] =>[orig_patent_app_number] => 10044724 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044724
Magnetoresistive random access memory (MRAM) with on-chip automatic determination of optimized write current method and apparatus Jan 9, 2002 Issued
Array ( [id] => 1359162 [patent_doc_number] => 06584023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'System for implementing a column redundancy scheme for arrays with controls that span multiple data bits' [patent_app_type] => B1 [patent_app_number] => 10/043024 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2320 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584023.pdf [firstpage_image] =>[orig_patent_app_number] => 10043024 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043024
System for implementing a column redundancy scheme for arrays with controls that span multiple data bits Jan 8, 2002 Issued
Array ( [id] => 1397978 [patent_doc_number] => 06556472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Static RAM with optimized timing of driving control signal for sense amplifier' [patent_app_type] => B2 [patent_app_number] => 10/038827 [patent_app_country] => US [patent_app_date] => 2002-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7253 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556472.pdf [firstpage_image] =>[orig_patent_app_number] => 10038827 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038827
Static RAM with optimized timing of driving control signal for sense amplifier Jan 7, 2002 Issued
Array ( [id] => 6371767 [patent_doc_number] => 20020118570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Method of read operation of nonvolatile semiconductor memory and nonvolatile semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/038828 [patent_app_country] => US [patent_app_date] => 2002-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12348 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118570.pdf [firstpage_image] =>[orig_patent_app_number] => 10038828 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038828
Method of read operation of nonvolatile semiconductor memory and nonvolatile semiconductor memory Jan 7, 2002 Issued
Array ( [id] => 1358517 [patent_doc_number] => 06580649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/038720 [patent_app_country] => US [patent_app_date] => 2002-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580649.pdf [firstpage_image] =>[orig_patent_app_number] => 10038720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038720
Semiconductor memory device Jan 7, 2002 Issued
Array ( [id] => 1593499 [patent_doc_number] => 06483739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => '4T memory with boost of stored voltage between standby and active' [patent_app_type] => B2 [patent_app_number] => 10/035923 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1640 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483739.pdf [firstpage_image] =>[orig_patent_app_number] => 10035923 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035923
4T memory with boost of stored voltage between standby and active Dec 30, 2001 Issued
Array ( [id] => 1303639 [patent_doc_number] => 06628540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Bias cell for four transistor (4T) SRAM operation' [patent_app_type] => B2 [patent_app_number] => 10/036324 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3861 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/628/06628540.pdf [firstpage_image] =>[orig_patent_app_number] => 10036324 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/036324
Bias cell for four transistor (4T) SRAM operation Dec 30, 2001 Issued
Array ( [id] => 1322748 [patent_doc_number] => 06608783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-19 [patent_title] => 'Twisted bit-line compensation' [patent_app_type] => B2 [patent_app_number] => 10/034625 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4967 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/608/06608783.pdf [firstpage_image] =>[orig_patent_app_number] => 10034625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034625
Twisted bit-line compensation Dec 26, 2001 Issued
Array ( [id] => 1376849 [patent_doc_number] => 06570794 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Twisted bit-line compensation for DRAM having redundancy' [patent_app_type] => B1 [patent_app_number] => 10/034626 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4969 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570794.pdf [firstpage_image] =>[orig_patent_app_number] => 10034626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034626
Twisted bit-line compensation for DRAM having redundancy Dec 26, 2001 Issued
Array ( [id] => 1413451 [patent_doc_number] => 06542398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Magnetic random access memory' [patent_app_type] => B2 [patent_app_number] => 10/033320 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2292 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542398.pdf [firstpage_image] =>[orig_patent_app_number] => 10033320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033320
Magnetic random access memory Dec 26, 2001 Issued
Array ( [id] => 6681967 [patent_doc_number] => 20030117831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Programmable conductor random access memory and a method for writing thereto' [patent_app_type] => new [patent_app_number] => 10/022722 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3492 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117831.pdf [firstpage_image] =>[orig_patent_app_number] => 10022722 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/022722
Programmable conductor random access memory and a method for writing thereto Dec 19, 2001 Issued
Array ( [id] => 1426137 [patent_doc_number] => 06510081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Electrically-eraseable programmable read-only memory having reduced-page-size program and erase' [patent_app_type] => B2 [patent_app_number] => 10/022314 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7884 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510081.pdf [firstpage_image] =>[orig_patent_app_number] => 10022314 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/022314
Electrically-eraseable programmable read-only memory having reduced-page-size program and erase Dec 17, 2001 Issued
Array ( [id] => 1531146 [patent_doc_number] => 06480416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Storage device counting error correction' [patent_app_type] => B2 [patent_app_number] => 10/020223 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3707 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480416.pdf [firstpage_image] =>[orig_patent_app_number] => 10020223 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020223
Storage device counting error correction Dec 17, 2001 Issued
Array ( [id] => 6534408 [patent_doc_number] => 20020110028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Apparatus and method for refreshing a flash memory unit' [patent_app_type] => new [patent_app_number] => 10/021824 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4077 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20020110028.pdf [firstpage_image] =>[orig_patent_app_number] => 10021824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/021824
Apparatus and method for refreshing a flash memory unit Dec 12, 2001 Issued
Array ( [id] => 5984066 [patent_doc_number] => 20020097620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Integrated memory having a cell array and charge equalization devices, and method for the accelerated writing of a datum to the integrated memory' [patent_app_type] => new [patent_app_number] => 10/015829 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4526 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20020097620.pdf [firstpage_image] =>[orig_patent_app_number] => 10015829 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015829
Integrated memory having a cell array and charge equalization devices, and method for the accelerated writing of a datum to the integrated memory Dec 12, 2001 Issued
Array ( [id] => 1511302 [patent_doc_number] => 06442055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'System and method for conserving power in a content addressable memory by providing an independent search line voltage' [patent_app_type] => B1 [patent_app_number] => 10/016025 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2269 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442055.pdf [firstpage_image] =>[orig_patent_app_number] => 10016025 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016025
System and method for conserving power in a content addressable memory by providing an independent search line voltage Dec 11, 2001 Issued
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