Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6597681 [patent_doc_number] => 20020085444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'MEMORY DEVICE AND METHOD FOR HANDLING OUT OF RANGE ADDRESSES' [patent_app_type] => new [patent_app_number] => 09/998824 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20020085444.pdf [firstpage_image] =>[orig_patent_app_number] => 09998824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998824
Memory device and method for handling out of range addresses Dec 2, 2001 Issued
Array ( [id] => 1593481 [patent_doc_number] => 06483734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Memory device having memory cells capable of four states' [patent_app_type] => B1 [patent_app_number] => 09/992426 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 7884 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483734.pdf [firstpage_image] =>[orig_patent_app_number] => 09992426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992426
Memory device having memory cells capable of four states Nov 25, 2001 Issued
Array ( [id] => 1411461 [patent_doc_number] => 06532164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'Magnetic spin polarization and magnetization rotation device with memory and writing process, using such a device' [patent_app_type] => B2 [patent_app_number] => 09/990321 [patent_app_country] => US [patent_app_date] => 2001-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4055 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532164.pdf [firstpage_image] =>[orig_patent_app_number] => 09990321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/990321
Magnetic spin polarization and magnetization rotation device with memory and writing process, using such a device Nov 22, 2001 Issued
Array ( [id] => 1315027 [patent_doc_number] => 06618301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Modular memory structure having adaptable redundancy circuitry' [patent_app_type] => B2 [patent_app_number] => 09/989425 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1636 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618301.pdf [firstpage_image] =>[orig_patent_app_number] => 09989425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989425
Modular memory structure having adaptable redundancy circuitry Nov 20, 2001 Issued
Array ( [id] => 1507462 [patent_doc_number] => 06466512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method of generating address configurations for solid state memory' [patent_app_type] => B1 [patent_app_number] => 09/990924 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6029 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466512.pdf [firstpage_image] =>[orig_patent_app_number] => 09990924 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/990924
Method of generating address configurations for solid state memory Nov 12, 2001 Issued
Array ( [id] => 1396501 [patent_doc_number] => 06560162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Memory cell decoder not including a charge pump' [patent_app_type] => B2 [patent_app_number] => 10/010625 [patent_app_country] => US [patent_app_date] => 2001-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5592 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560162.pdf [firstpage_image] =>[orig_patent_app_number] => 10010625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010625
Memory cell decoder not including a charge pump Nov 7, 2001 Issued
Array ( [id] => 1285219 [patent_doc_number] => 06646907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/985724 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 34 [patent_no_of_words] => 9831 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646907.pdf [firstpage_image] =>[orig_patent_app_number] => 09985724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/985724
Semiconductor memory device Nov 5, 2001 Issued
Array ( [id] => 1538611 [patent_doc_number] => 06490207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'Delay-locked loop with binary-coupled capacitor' [patent_app_type] => B2 [patent_app_number] => 10/033574 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7293 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490207.pdf [firstpage_image] =>[orig_patent_app_number] => 10033574 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033574
Delay-locked loop with binary-coupled capacitor Nov 1, 2001 Issued
Array ( [id] => 6596550 [patent_doc_number] => 20020085411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Method for preventing unwanted programming in an MRAM configuration' [patent_app_type] => new [patent_app_number] => 09/999324 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3123 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20020085411.pdf [firstpage_image] =>[orig_patent_app_number] => 09999324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/999324
Method for preventing unwanted programming in an MRAM configuration Oct 30, 2001 Issued
Array ( [id] => 1572672 [patent_doc_number] => 06498751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-24 [patent_title] => 'Fast sense amplifier for nonvolatile memories' [patent_app_type] => B2 [patent_app_number] => 09/999325 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2413 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498751.pdf [firstpage_image] =>[orig_patent_app_number] => 09999325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/999325
Fast sense amplifier for nonvolatile memories Oct 30, 2001 Issued
Array ( [id] => 5934637 [patent_doc_number] => 20020060925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Dram memory cell' [patent_app_type] => new [patent_app_number] => 09/999326 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1703 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060925.pdf [firstpage_image] =>[orig_patent_app_number] => 09999326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/999326
DRAM memory cell Oct 30, 2001 Issued
Array ( [id] => 6868794 [patent_doc_number] => 20030081483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'DRAM REFRESH COMMAND OPERATION' [patent_app_type] => new [patent_app_number] => 09/984626 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4305 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20030081483.pdf [firstpage_image] =>[orig_patent_app_number] => 09984626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984626
DRAM refresh command operation Oct 29, 2001 Issued
Array ( [id] => 7626080 [patent_doc_number] => 06768686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Read/write amplifier for a DRAM memory cell, and DRAM memory' [patent_app_type] => B2 [patent_app_number] => 10/001429 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8094 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768686.pdf [firstpage_image] =>[orig_patent_app_number] => 10001429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001429
Read/write amplifier for a DRAM memory cell, and DRAM memory Oct 29, 2001 Issued
Array ( [id] => 6519846 [patent_doc_number] => 20020136049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method for sensing data stored in a ferroelectric random access memory device' [patent_app_type] => new [patent_app_number] => 10/003528 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4076 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20020136049.pdf [firstpage_image] =>[orig_patent_app_number] => 10003528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003528
Method for sensing data stored in a ferroelectric random access memory device Oct 29, 2001 Issued
Array ( [id] => 1531141 [patent_doc_number] => 06480415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/984224 [patent_app_country] => US [patent_app_date] => 2001-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 11612 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480415.pdf [firstpage_image] =>[orig_patent_app_number] => 09984224 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984224
Nonvolatile semiconductor memory device Oct 28, 2001 Issued
Array ( [id] => 6239847 [patent_doc_number] => 20020044475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Dynamic content addressable memory cell' [patent_app_type] => new [patent_app_number] => 09/977982 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6605 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20020044475.pdf [firstpage_image] =>[orig_patent_app_number] => 09977982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977982
Dynamic content addressable memory cell Oct 16, 2001 Issued
Array ( [id] => 7610466 [patent_doc_number] => 06842392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Activation of word lines in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 09/976021 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 174 [patent_no_of_words] => 13485 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842392.pdf [firstpage_image] =>[orig_patent_app_number] => 09976021 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976021
Activation of word lines in semiconductor memory device Oct 14, 2001 Issued
Array ( [id] => 1258884 [patent_doc_number] => 06667911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'High speed memory architecture' [patent_app_type] => B2 [patent_app_number] => 09/973860 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4714 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667911.pdf [firstpage_image] =>[orig_patent_app_number] => 09973860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973860
High speed memory architecture Oct 10, 2001 Issued
Array ( [id] => 1428228 [patent_doc_number] => 06507514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Integrated circuit memory chip for use in single or multi-chip packaging' [patent_app_type] => B1 [patent_app_number] => 09/974227 [patent_app_country] => US [patent_app_date] => 2001-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 9754 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507514.pdf [firstpage_image] =>[orig_patent_app_number] => 09974227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974227
Integrated circuit memory chip for use in single or multi-chip packaging Oct 9, 2001 Issued
Array ( [id] => 1429377 [patent_doc_number] => 06515909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Flash memory device with a variable erase pulse' [patent_app_type] => B1 [patent_app_number] => 09/972426 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8680 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515909.pdf [firstpage_image] =>[orig_patent_app_number] => 09972426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972426
Flash memory device with a variable erase pulse Oct 4, 2001 Issued
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