
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1550216
[patent_doc_number] => 06445608
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Ferroelectric random access memory configurable output driver circuit'
[patent_app_type] => B1
[patent_app_number] => 09/950560
[patent_app_country] => US
[patent_app_date] => 2001-09-10
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[pdf_file] => patents/06/445/06445608.pdf
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Array
(
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[patent_doc_number] => 20020145927
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[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Semiconductor integrated circuit device and data-write method thereof'
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[patent_app_number] => 09/947459
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Array
(
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[patent_issue_date] => 2002-03-07
[patent_title] => 'Circuit and method for supplying internal power to semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 09/946561
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[patent_app_date] => 2001-09-06
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Array
(
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[patent_issue_date] => 2002-09-10
[patent_title] => 'Voltage driver for a memory'
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[patent_app_number] => 09/945021
[patent_app_country] => US
[patent_app_date] => 2001-08-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/945021 | Voltage driver for a memory | Aug 30, 2001 | Issued |
Array
(
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[patent_doc_number] => 06538951
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[patent_issue_date] => 2003-03-25
[patent_title] => 'Dram active termination control'
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Array
(
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[patent_doc_number] => 20040041173
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[patent_title] => 'Semiconductor storage and its refreshing method'
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Array
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[patent_title] => 'Read-out circuit'
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Array
(
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[patent_issue_date] => 2006-04-25
[patent_title] => 'Semiconductor memory device and its test method as well as test circuit'
[patent_app_type] => utility
[patent_app_number] => 10/362891
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/362891 | Semiconductor memory device and its test method as well as test circuit | Aug 29, 2001 | Issued |
Array
(
[id] => 6350280
[patent_doc_number] => 20020057109
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[patent_issue_date] => 2002-05-16
[patent_title] => 'Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit'
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Array
(
[id] => 1550230
[patent_doc_number] => 06445612
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[patent_title] => 'MRAM with midpoint generator reference and method for readout'
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Array
(
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[patent_title] => 'Three step write process used for a nonvolatile NOR type EEPROM memory'
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Array
(
[id] => 1341975
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[patent_title] => 'Offset compensated sensing for magnetic random access memory'
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Array
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Array
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Array
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