Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1550216 [patent_doc_number] => 06445608 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Ferroelectric random access memory configurable output driver circuit' [patent_app_type] => B1 [patent_app_number] => 09/950560 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445608.pdf [firstpage_image] =>[orig_patent_app_number] => 09950560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950560
Ferroelectric random access memory configurable output driver circuit Sep 9, 2001 Issued
Array ( [id] => 6155738 [patent_doc_number] => 20020145927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Semiconductor integrated circuit device and data-write method thereof' [patent_app_type] => new [patent_app_number] => 09/947459 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7697 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145927.pdf [firstpage_image] =>[orig_patent_app_number] => 09947459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947459
Semiconductor integrated circuit device and data-write method thereof Sep 6, 2001 Issued
Array ( [id] => 5997075 [patent_doc_number] => 20020027234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Circuit and method for supplying internal power to semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/946561 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027234.pdf [firstpage_image] =>[orig_patent_app_number] => 09946561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946561
Circuit and method for supplying internal power to semiconductor memory device Sep 5, 2001 Issued
Array ( [id] => 1582574 [patent_doc_number] => 06449211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Voltage driver for a memory' [patent_app_type] => B1 [patent_app_number] => 09/945021 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1752 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449211.pdf [firstpage_image] =>[orig_patent_app_number] => 09945021 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945021
Voltage driver for a memory Aug 30, 2001 Issued
Array ( [id] => 1417096 [patent_doc_number] => 06538951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Dram active termination control' [patent_app_type] => B1 [patent_app_number] => 09/941649 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2473 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538951.pdf [firstpage_image] =>[orig_patent_app_number] => 09941649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941649
Dram active termination control Aug 29, 2001 Issued
Array ( [id] => 7130144 [patent_doc_number] => 20040041173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Semiconductor storage and its refreshing method' [patent_app_type] => new [patent_app_number] => 10/363298 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14358 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041173.pdf [firstpage_image] =>[orig_patent_app_number] => 10363298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/363298
Semiconductor storage and its refreshing method Aug 29, 2001 Issued
Array ( [id] => 6397166 [patent_doc_number] => 20020036518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Read-out circuit' [patent_app_type] => new [patent_app_number] => 09/941722 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10610 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20020036518.pdf [firstpage_image] =>[orig_patent_app_number] => 09941722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941722
Read-out circuit Aug 29, 2001 Issued
Array ( [id] => 741566 [patent_doc_number] => 07035154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Semiconductor memory device and its test method as well as test circuit' [patent_app_type] => utility [patent_app_number] => 10/362891 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9413 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035154.pdf [firstpage_image] =>[orig_patent_app_number] => 10362891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/362891
Semiconductor memory device and its test method as well as test circuit Aug 29, 2001 Issued
Array ( [id] => 6350280 [patent_doc_number] => 20020057109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit' [patent_app_type] => new [patent_app_number] => 09/940597 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11712 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20020057109.pdf [firstpage_image] =>[orig_patent_app_number] => 09940597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940597
Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit Aug 28, 2001 Issued
Array ( [id] => 1550230 [patent_doc_number] => 06445612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'MRAM with midpoint generator reference and method for readout' [patent_app_type] => B1 [patent_app_number] => 09/940320 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5015 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445612.pdf [firstpage_image] =>[orig_patent_app_number] => 09940320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940320
MRAM with midpoint generator reference and method for readout Aug 26, 2001 Issued
Array ( [id] => 1572675 [patent_doc_number] => 06498752 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Three step write process used for a nonvolatile NOR type EEPROM memory' [patent_app_type] => B1 [patent_app_number] => 09/940159 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 6739 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498752.pdf [firstpage_image] =>[orig_patent_app_number] => 09940159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940159
Three step write process used for a nonvolatile NOR type EEPROM memory Aug 26, 2001 Issued
Array ( [id] => 1341975 [patent_doc_number] => 06597600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Offset compensated sensing for magnetic random access memory' [patent_app_type] => B2 [patent_app_number] => 09/938722 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4353 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597600.pdf [firstpage_image] =>[orig_patent_app_number] => 09938722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938722
Offset compensated sensing for magnetic random access memory Aug 26, 2001 Issued
Array ( [id] => 1442596 [patent_doc_number] => 06496420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Methods and apparatus for reading memory device register data' [patent_app_type] => B2 [patent_app_number] => 09/938809 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6269 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496420.pdf [firstpage_image] =>[orig_patent_app_number] => 09938809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938809
Methods and apparatus for reading memory device register data Aug 23, 2001 Issued
Array ( [id] => 1517647 [patent_doc_number] => 06421271 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'MRAM configuration' [patent_app_type] => B1 [patent_app_number] => 09/935622 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2977 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421271.pdf [firstpage_image] =>[orig_patent_app_number] => 09935622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935622
MRAM configuration Aug 22, 2001 Issued
Array ( [id] => 1523347 [patent_doc_number] => 06414880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Multiple line buffer type memory LSI' [patent_app_type] => B1 [patent_app_number] => 09/933820 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 12453 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414880.pdf [firstpage_image] =>[orig_patent_app_number] => 09933820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933820
Multiple line buffer type memory LSI Aug 21, 2001 Issued
Array ( [id] => 6584768 [patent_doc_number] => 20020041533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Fuse circuit using anti-fuse and method for searching for failed address in semiconductor memory' [patent_app_type] => new [patent_app_number] => 09/931024 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12935 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041533.pdf [firstpage_image] =>[orig_patent_app_number] => 09931024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/931024
Fuse circuit using anti-fuse and method for searching for failed address in semiconductor memory Aug 16, 2001 Issued
Array ( [id] => 5998441 [patent_doc_number] => 20020027800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Variable voltage isolation gate and method' [patent_app_type] => new [patent_app_number] => 09/929611 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2716 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027800.pdf [firstpage_image] =>[orig_patent_app_number] => 09929611 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929611
Variable voltage isolation gate and method Aug 13, 2001 Issued
Array ( [id] => 1429208 [patent_doc_number] => 06515888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Low cost three-dimensional memory array' [patent_app_type] => B2 [patent_app_number] => 09/928969 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6185 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515888.pdf [firstpage_image] =>[orig_patent_app_number] => 09928969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928969
Low cost three-dimensional memory array Aug 12, 2001 Issued
Array ( [id] => 1397905 [patent_doc_number] => 06556468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'High bit density, high speed, via and metal programmable read only memory core cell architecture' [patent_app_type] => B2 [patent_app_number] => 09/917226 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2910 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556468.pdf [firstpage_image] =>[orig_patent_app_number] => 09917226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917226
High bit density, high speed, via and metal programmable read only memory core cell architecture Jul 26, 2001 Issued
Array ( [id] => 5887292 [patent_doc_number] => 20020012284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Semiconductor memory device and method for accessing memory cell' [patent_app_type] => new [patent_app_number] => 09/911120 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 18618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20020012284.pdf [firstpage_image] =>[orig_patent_app_number] => 09911120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911120
Semiconductor memory device and method for accessing memory cell Jul 22, 2001 Issued
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