Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1520400 [patent_doc_number] => 06501668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/907920 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 1901 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501668.pdf [firstpage_image] =>[orig_patent_app_number] => 09907920 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907920
Semiconductor memory device Jul 18, 2001 Issued
Array ( [id] => 6999319 [patent_doc_number] => 20010053100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Delay-locked loop with binary-coupled capacitor' [patent_app_type] => new [patent_app_number] => 09/907316 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7391 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053100.pdf [firstpage_image] =>[orig_patent_app_number] => 09907316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907316
Delay-locked loop with binary-coupled capacitor Jul 15, 2001 Issued
Array ( [id] => 7962109 [patent_doc_number] => 06681375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Check system for wiring structure of printed circuit board' [patent_app_type] => B2 [patent_app_number] => 09/905451 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4482 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681375.pdf [firstpage_image] =>[orig_patent_app_number] => 09905451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905451
Check system for wiring structure of printed circuit board Jul 12, 2001 Issued
Array ( [id] => 1480080 [patent_doc_number] => 06344993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Dual floating gate EEPROM cell array with steering gates shared by adjacent cells' [patent_app_type] => B1 [patent_app_number] => 09/904945 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9633 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344993.pdf [firstpage_image] =>[orig_patent_app_number] => 09904945 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904945
Dual floating gate EEPROM cell array with steering gates shared by adjacent cells Jul 12, 2001 Issued
Array ( [id] => 1431635 [patent_doc_number] => 06504740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Content addressable memory having compare data transition detector' [patent_app_type] => B1 [patent_app_number] => 09/904326 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2254 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504740.pdf [firstpage_image] =>[orig_patent_app_number] => 09904326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904326
Content addressable memory having compare data transition detector Jul 11, 2001 Issued
Array ( [id] => 7646427 [patent_doc_number] => 06477093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Semiconductor memory and method of operating same' [patent_app_type] => B2 [patent_app_number] => 09/901628 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4202 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477093.pdf [firstpage_image] =>[orig_patent_app_number] => 09901628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901628
Semiconductor memory and method of operating same Jul 10, 2001 Issued
Array ( [id] => 1555135 [patent_doc_number] => 06400620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Semiconductor memory device with burn-in test function' [patent_app_type] => B1 [patent_app_number] => 09/900728 [patent_app_country] => US [patent_app_date] => 2001-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2577 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400620.pdf [firstpage_image] =>[orig_patent_app_number] => 09900728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/900728
Semiconductor memory device with burn-in test function Jul 5, 2001 Issued
Array ( [id] => 1593565 [patent_doc_number] => 06483752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Erase method for nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/898022 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 12835 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483752.pdf [firstpage_image] =>[orig_patent_app_number] => 09898022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898022
Erase method for nonvolatile semiconductor memory device Jul 4, 2001 Issued
Array ( [id] => 1593629 [patent_doc_number] => 06483768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Current driver configuration for MRAM' [patent_app_type] => B2 [patent_app_number] => 09/898221 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2789 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483768.pdf [firstpage_image] =>[orig_patent_app_number] => 09898221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898221
Current driver configuration for MRAM Jul 2, 2001 Issued
Array ( [id] => 1431666 [patent_doc_number] => 06504751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Integrated memory having memory cells with a magnetoresistive storage property and method of operating such a memory' [patent_app_type] => B2 [patent_app_number] => 09/898224 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3039 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504751.pdf [firstpage_image] =>[orig_patent_app_number] => 09898224 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898224
Integrated memory having memory cells with a magnetoresistive storage property and method of operating such a memory Jul 2, 2001 Issued
Array ( [id] => 7644638 [patent_doc_number] => 06473335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'MRAM configuration' [patent_app_type] => B2 [patent_app_number] => 09/898222 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3124 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473335.pdf [firstpage_image] =>[orig_patent_app_number] => 09898222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898222
MRAM configuration Jul 2, 2001 Issued
Array ( [id] => 1593588 [patent_doc_number] => 06483757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Delay-locked loop with binary-coupled capacitor' [patent_app_type] => B2 [patent_app_number] => 09/895503 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7314 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483757.pdf [firstpage_image] =>[orig_patent_app_number] => 09895503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895503
Delay-locked loop with binary-coupled capacitor Jun 28, 2001 Issued
Array ( [id] => 1390067 [patent_doc_number] => 06563749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Dynamic memory circuit including spare cells' [patent_app_type] => B2 [patent_app_number] => 09/895026 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3312 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563749.pdf [firstpage_image] =>[orig_patent_app_number] => 09895026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895026
Dynamic memory circuit including spare cells Jun 28, 2001 Issued
Array ( [id] => 6028767 [patent_doc_number] => 20020017688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Semiconductor memory circuit' [patent_app_type] => new [patent_app_number] => 09/888620 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3306 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20020017688.pdf [firstpage_image] =>[orig_patent_app_number] => 09888620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888620
Semiconductor memory circuit Jun 25, 2001 Issued
Array ( [id] => 1413768 [patent_doc_number] => 06542418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Redundant memory array having dual-use repair elements' [patent_app_type] => B2 [patent_app_number] => 09/892026 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542418.pdf [firstpage_image] =>[orig_patent_app_number] => 09892026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892026
Redundant memory array having dual-use repair elements Jun 25, 2001 Issued
Array ( [id] => 1384680 [patent_doc_number] => 06567336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Semiconductor memory for logic-hybrid memory' [patent_app_type] => B2 [patent_app_number] => 09/888649 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4079 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567336.pdf [firstpage_image] =>[orig_patent_app_number] => 09888649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888649
Semiconductor memory for logic-hybrid memory Jun 25, 2001 Issued
Array ( [id] => 1377045 [patent_doc_number] => 06570806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor' [patent_app_type] => B2 [patent_app_number] => 09/891025 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4923 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570806.pdf [firstpage_image] =>[orig_patent_app_number] => 09891025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891025
System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor Jun 24, 2001 Issued
Array ( [id] => 6223046 [patent_doc_number] => 20020003728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Integrated memory with redundancy and method for repairing an integrated memory' [patent_app_type] => new [patent_app_number] => 09/888022 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4642 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003728.pdf [firstpage_image] =>[orig_patent_app_number] => 09888022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888022
Integrated memory with redundancy and method for repairing an integrated memory Jun 21, 2001 Issued
Array ( [id] => 1550296 [patent_doc_number] => 06445627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/886026 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 12461 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445627.pdf [firstpage_image] =>[orig_patent_app_number] => 09886026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886026
Semiconductor integrated circuit Jun 21, 2001 Issued
Array ( [id] => 1382933 [patent_doc_number] => 06574784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Short edge management in rule based OPC' [patent_app_type] => B1 [patent_app_number] => 09/882802 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 4496 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574784.pdf [firstpage_image] =>[orig_patent_app_number] => 09882802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882802
Short edge management in rule based OPC Jun 13, 2001 Issued
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