
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1520400
[patent_doc_number] => 06501668
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-31
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 09/907920
[patent_app_country] => US
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[pdf_file] => patents/06/501/06501668.pdf
[firstpage_image] =>[orig_patent_app_number] => 09907920
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Array
(
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[patent_issue_date] => 2001-12-20
[patent_title] => 'Delay-locked loop with binary-coupled capacitor'
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Array
(
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[patent_doc_number] => 06681375
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[patent_issue_date] => 2004-01-20
[patent_title] => 'Check system for wiring structure of printed circuit board'
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[patent_app_date] => 2001-07-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/905451 | Check system for wiring structure of printed circuit board | Jul 12, 2001 | Issued |
Array
(
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[patent_doc_number] => 06344993
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[patent_kind] => B1
[patent_issue_date] => 2002-02-05
[patent_title] => 'Dual floating gate EEPROM cell array with steering gates shared by adjacent cells'
[patent_app_type] => B1
[patent_app_number] => 09/904945
[patent_app_country] => US
[patent_app_date] => 2001-07-13
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[pdf_file] => patents/06/344/06344993.pdf
[firstpage_image] =>[orig_patent_app_number] => 09904945
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/904945 | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells | Jul 12, 2001 | Issued |
Array
(
[id] => 1431635
[patent_doc_number] => 06504740
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-07
[patent_title] => 'Content addressable memory having compare data transition detector'
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[patent_app_number] => 09/904326
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[firstpage_image] =>[orig_patent_app_number] => 09904326
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/904326 | Content addressable memory having compare data transition detector | Jul 11, 2001 | Issued |
Array
(
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[patent_doc_number] => 06477093
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-05
[patent_title] => 'Semiconductor memory and method of operating same'
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[patent_app_number] => 09/901628
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Array
(
[id] => 1555135
[patent_doc_number] => 06400620
[patent_country] => US
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[patent_issue_date] => 2002-06-04
[patent_title] => 'Semiconductor memory device with burn-in test function'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/900728 | Semiconductor memory device with burn-in test function | Jul 5, 2001 | Issued |
Array
(
[id] => 1593565
[patent_doc_number] => 06483752
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-19
[patent_title] => 'Erase method for nonvolatile semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 09/898022
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/898022 | Erase method for nonvolatile semiconductor memory device | Jul 4, 2001 | Issued |
Array
(
[id] => 1593629
[patent_doc_number] => 06483768
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-19
[patent_title] => 'Current driver configuration for MRAM'
[patent_app_type] => B2
[patent_app_number] => 09/898221
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/898221 | Current driver configuration for MRAM | Jul 2, 2001 | Issued |
Array
(
[id] => 1431666
[patent_doc_number] => 06504751
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[patent_issue_date] => 2003-01-07
[patent_title] => 'Integrated memory having memory cells with a magnetoresistive storage property and method of operating such a memory'
[patent_app_type] => B2
[patent_app_number] => 09/898224
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/898224 | Integrated memory having memory cells with a magnetoresistive storage property and method of operating such a memory | Jul 2, 2001 | Issued |
Array
(
[id] => 7644638
[patent_doc_number] => 06473335
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[patent_title] => 'MRAM configuration'
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Array
(
[id] => 1593588
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[patent_title] => 'Delay-locked loop with binary-coupled capacitor'
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Array
(
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[patent_title] => 'Dynamic memory circuit including spare cells'
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Array
(
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Array
(
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Array
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Array
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[patent_title] => 'System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor'
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(
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Array
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Array
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