Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1511455 [patent_doc_number] => 06442102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and apparatus for implementing high speed DDR SDRAM read interface with reduced ACLV effects' [patent_app_type] => B1 [patent_app_number] => 09/825825 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2062 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442102.pdf [firstpage_image] =>[orig_patent_app_number] => 09825825 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/825825
Method and apparatus for implementing high speed DDR SDRAM read interface with reduced ACLV effects Apr 3, 2001 Issued
Array ( [id] => 1564230 [patent_doc_number] => 06438032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Non-volatile memory with peak current noise reduction' [patent_app_type] => B1 [patent_app_number] => 09/818426 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7299 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438032.pdf [firstpage_image] =>[orig_patent_app_number] => 09818426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818426
Non-volatile memory with peak current noise reduction Mar 26, 2001 Issued
Array ( [id] => 7014542 [patent_doc_number] => 20010051402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Ferroelectric random access memory (FRAM) device and method for controlling read/write operations thereof' [patent_app_type] => new [patent_app_number] => 09/819125 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4423 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051402.pdf [firstpage_image] =>[orig_patent_app_number] => 09819125 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819125
Ferroelectric random access memory (FRAM) device and method for controlling read/write operations thereof Mar 26, 2001 Issued
Array ( [id] => 1550308 [patent_doc_number] => 06445630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method for carrying out a burn-in process for electrically stressing a semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 09/816924 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2348 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445630.pdf [firstpage_image] =>[orig_patent_app_number] => 09816924 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816924
Method for carrying out a burn-in process for electrically stressing a semiconductor memory Mar 22, 2001 Issued
Array ( [id] => 6884393 [patent_doc_number] => 20010038552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Semiconductor memory with switches for reducing leakage current' [patent_app_type] => new [patent_app_number] => 09/814724 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3270 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20010038552.pdf [firstpage_image] =>[orig_patent_app_number] => 09814724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814724
Semiconductor memory with switches for reducing leakage current Mar 22, 2001 Abandoned
Array ( [id] => 1578318 [patent_doc_number] => 06469935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Array architecture nonvolatile memory and its operation methods' [patent_app_type] => B2 [patent_app_number] => 09/810122 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7521 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469935.pdf [firstpage_image] =>[orig_patent_app_number] => 09810122 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810122
Array architecture nonvolatile memory and its operation methods Mar 18, 2001 Issued
Array ( [id] => 1599707 [patent_doc_number] => 06385099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Reducing level shifter standby power consumption' [patent_app_type] => B1 [patent_app_number] => 09/811025 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1672 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385099.pdf [firstpage_image] =>[orig_patent_app_number] => 09811025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811025
Reducing level shifter standby power consumption Mar 15, 2001 Issued
Array ( [id] => 1603899 [patent_doc_number] => 06434082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock' [patent_app_type] => B1 [patent_app_number] => 09/805420 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 5772 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434082.pdf [firstpage_image] =>[orig_patent_app_number] => 09805420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805420
Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock Mar 12, 2001 Issued
Array ( [id] => 1578309 [patent_doc_number] => 06469932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Memory with row redundancy' [patent_app_type] => B2 [patent_app_number] => 09/804125 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4893 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469932.pdf [firstpage_image] =>[orig_patent_app_number] => 09804125 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804125
Memory with row redundancy Mar 11, 2001 Issued
Array ( [id] => 1482886 [patent_doc_number] => 06452836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Non-volatile memory device with erase cycle register' [patent_app_type] => B1 [patent_app_number] => 09/803623 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4588 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452836.pdf [firstpage_image] =>[orig_patent_app_number] => 09803623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803623
Non-volatile memory device with erase cycle register Mar 8, 2001 Issued
Array ( [id] => 6947485 [patent_doc_number] => 20010021119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Buffer circuit, and semiconductor device and semiconductor memory device including same' [patent_app_type] => new [patent_app_number] => 09/803626 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5293 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021119.pdf [firstpage_image] =>[orig_patent_app_number] => 09803626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803626
Buffer circuit, and semiconductor device and semiconductor memory device including same Mar 8, 2001 Issued
Array ( [id] => 6933915 [patent_doc_number] => 20010055259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Digital signal recording/reproducing method' [patent_app_type] => new [patent_app_number] => 09/797804 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8097 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20010055259.pdf [firstpage_image] =>[orig_patent_app_number] => 09797804 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797804
Digital signal recording/reproducing method Mar 4, 2001 Issued
Array ( [id] => 1555110 [patent_doc_number] => 06400613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Positive write masking method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/799222 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6937 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400613.pdf [firstpage_image] =>[orig_patent_app_number] => 09799222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/799222
Positive write masking method and apparatus Mar 4, 2001 Issued
Array ( [id] => 5903548 [patent_doc_number] => 20020141239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'SPLIT COMMON SOURCE ON EEPROM ARRAY' [patent_app_type] => new [patent_app_number] => 09/799328 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3487 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20020141239.pdf [firstpage_image] =>[orig_patent_app_number] => 09799328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/799328
Split common source on EEPROM array Mar 4, 2001 Issued
Array ( [id] => 6895679 [patent_doc_number] => 20010026469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Integrated memory having memory cells with magnetoresistive storage effect' [patent_app_type] => new [patent_app_number] => 09/799626 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2548 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026469.pdf [firstpage_image] =>[orig_patent_app_number] => 09799626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/799626
Integrated memory having memory cells with magnetoresistive storage effect Mar 4, 2001 Issued
Array ( [id] => 1135710 [patent_doc_number] => 06788593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Asynchronous, high-bandwidth memory component using calibrated timing elements' [patent_app_type] => B2 [patent_app_number] => 09/796924 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 38 [patent_no_of_words] => 19115 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788593.pdf [firstpage_image] =>[orig_patent_app_number] => 09796924 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796924
Asynchronous, high-bandwidth memory component using calibrated timing elements Feb 27, 2001 Issued
Array ( [id] => 1546877 [patent_doc_number] => 06373758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'System and method of operating a programmable column fail counter for redundancy allocation' [patent_app_type] => B1 [patent_app_number] => 09/792320 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373758.pdf [firstpage_image] =>[orig_patent_app_number] => 09792320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792320
System and method of operating a programmable column fail counter for redundancy allocation Feb 22, 2001 Issued
Array ( [id] => 6947502 [patent_doc_number] => 20010021136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods' [patent_app_type] => new [patent_app_number] => 09/792421 [patent_app_country] => US [patent_app_date] => 2001-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3946 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021136.pdf [firstpage_image] =>[orig_patent_app_number] => 09792421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792421
Auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods Feb 22, 2001 Issued
Array ( [id] => 6891642 [patent_doc_number] => 20010017804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Semiconductor device, semiconductor memory device and test-mode entry method' [patent_app_type] => new [patent_app_number] => 09/789727 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4319 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017804.pdf [firstpage_image] =>[orig_patent_app_number] => 09789727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789727
Semiconductor device, semiconductor memory device and test-mode entry method Feb 21, 2001 Issued
Array ( [id] => 1463724 [patent_doc_number] => 06392927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-21 [patent_title] => 'Cell array, operating method of the same and manufacturing method of the same' [patent_app_type] => B2 [patent_app_number] => 09/789726 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 6215 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392927.pdf [firstpage_image] =>[orig_patent_app_number] => 09789726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789726
Cell array, operating method of the same and manufacturing method of the same Feb 21, 2001 Issued
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