
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7392500
[patent_doc_number] => 20040017699
[patent_country] => US
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[patent_issue_date] => 2004-01-29
[patent_title] => 'Semiconductor memory device in which data are read and written asynchronously with application of address signal'
[patent_app_type] => new
[patent_app_number] => 09/789763
[patent_app_country] => US
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[pdf_file] => publications/A1/0017/20040017699.pdf
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Array
(
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[patent_doc_number] => 06434044
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[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Method and system for generation and distribution of supply voltages in memory systems'
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[patent_app_date] => 2001-02-16
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Array
(
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[patent_issue_date] => 2002-09-26
[patent_title] => 'Memory array organization for static arrays'
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[patent_app_number] => 09/784828
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Array
(
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[patent_doc_number] => 20010021134
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[patent_issue_date] => 2001-09-13
[patent_title] => 'Integrated semiconductor memory with redundant units for memory cells'
[patent_app_type] => new
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[patent_app_date] => 2001-02-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/780326 | Integrated semiconductor memory with redundant units for memory cells | Feb 8, 2001 | Issued |
Array
(
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[patent_doc_number] => 06563754
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[patent_issue_date] => 2003-05-13
[patent_title] => 'DRAM circuit with separate refresh memory'
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Array
(
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[patent_issue_date] => 2002-05-07
[patent_title] => 'Semiconductor memory device having a circuit for testing memories'
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Array
(
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[patent_title] => 'Serial access memory and data write/read method'
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Array
(
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[patent_issue_date] => 2002-04-02
[patent_title] => 'Circuit configuration for generating an output clock signal with optimized signal generation time'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/773220 | Circuit configuration for generating an output clock signal with optimized signal generation time | Jan 30, 2001 | Issued |
Array
(
[id] => 1478555
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[patent_title] => 'Memory component with short access time'
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Array
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[patent_title] => 'Method and circuit configuration for read-write mode control of a synchronous memory'
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Array
(
[id] => 1478428
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[patent_title] => 'Method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure'
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Array
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Array
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Array
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Array
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