Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7392500 [patent_doc_number] => 20040017699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Semiconductor memory device in which data are read and written asynchronously with application of address signal' [patent_app_type] => new [patent_app_number] => 09/789763 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7978 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017699.pdf [firstpage_image] =>[orig_patent_app_number] => 09789763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789763
Semiconductor memory device in which data are read and written asynchronously with application of address signal Feb 21, 2001 Issued
Array ( [id] => 1603861 [patent_doc_number] => 06434044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and system for generation and distribution of supply voltages in memory systems' [patent_app_type] => B1 [patent_app_number] => 09/788120 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5027 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434044.pdf [firstpage_image] =>[orig_patent_app_number] => 09788120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788120
Method and system for generation and distribution of supply voltages in memory systems Feb 15, 2001 Issued
Array ( [id] => 6520019 [patent_doc_number] => 20020136062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Memory array organization for static arrays' [patent_app_type] => new [patent_app_number] => 09/784828 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2266 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20020136062.pdf [firstpage_image] =>[orig_patent_app_number] => 09784828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/784828
Memory array organization for static arrays Feb 14, 2001 Issued
Array ( [id] => 6947500 [patent_doc_number] => 20010021134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Integrated semiconductor memory with redundant units for memory cells' [patent_app_type] => new [patent_app_number] => 09/780326 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3685 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021134.pdf [firstpage_image] =>[orig_patent_app_number] => 09780326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780326
Integrated semiconductor memory with redundant units for memory cells Feb 8, 2001 Issued
Array ( [id] => 1390175 [patent_doc_number] => 06563754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'DRAM circuit with separate refresh memory' [patent_app_type] => B1 [patent_app_number] => 09/781524 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563754.pdf [firstpage_image] =>[orig_patent_app_number] => 09781524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781524
DRAM circuit with separate refresh memory Feb 7, 2001 Issued
Array ( [id] => 1599720 [patent_doc_number] => 06385103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Semiconductor memory device having a circuit for testing memories' [patent_app_type] => B1 [patent_app_number] => 09/773622 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4824 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385103.pdf [firstpage_image] =>[orig_patent_app_number] => 09773622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773622
Semiconductor memory device having a circuit for testing memories Feb 1, 2001 Issued
Array ( [id] => 6933678 [patent_doc_number] => 20010055022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Serial access memory and data write/read method' [patent_app_type] => new [patent_app_number] => 09/773024 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17782 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20010055022.pdf [firstpage_image] =>[orig_patent_app_number] => 09773024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773024
Serial access memory and data write/read method Jan 31, 2001 Abandoned
Array ( [id] => 1488667 [patent_doc_number] => 06366527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-02 [patent_title] => 'Circuit configuration for generating an output clock signal with optimized signal generation time' [patent_app_type] => B2 [patent_app_number] => 09/773220 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3619 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366527.pdf [firstpage_image] =>[orig_patent_app_number] => 09773220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773220
Circuit configuration for generating an output clock signal with optimized signal generation time Jan 30, 2001 Issued
Array ( [id] => 1478555 [patent_doc_number] => 06388944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Memory component with short access time' [patent_app_type] => B2 [patent_app_number] => 09/773221 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2501 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388944.pdf [firstpage_image] =>[orig_patent_app_number] => 09773221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773221
Memory component with short access time Jan 30, 2001 Issued
Array ( [id] => 7064217 [patent_doc_number] => 20010043503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Method and circuit configuration for read-write mode control of a synchronous memory' [patent_app_type] => new [patent_app_number] => 09/773222 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2166 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043503.pdf [firstpage_image] =>[orig_patent_app_number] => 09773222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773222
Method and circuit configuration for read-write mode control of a synchronous memory Jan 30, 2001 Issued
Array ( [id] => 1478428 [patent_doc_number] => 06388913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure' [patent_app_type] => B1 [patent_app_number] => 09/772326 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2039 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388913.pdf [firstpage_image] =>[orig_patent_app_number] => 09772326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772326
Method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure Jan 29, 2001 Issued
Array ( [id] => 1478546 [patent_doc_number] => 06388943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Differential clock crossing point level-shifting device' [patent_app_type] => B1 [patent_app_number] => 09/772420 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4684 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388943.pdf [firstpage_image] =>[orig_patent_app_number] => 09772420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772420
Differential clock crossing point level-shifting device Jan 28, 2001 Issued
Array ( [id] => 6882161 [patent_doc_number] => 20010048633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Semiconductor memory circuit including a data output circuit' [patent_app_type] => new [patent_app_number] => 09/769425 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7151 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048633.pdf [firstpage_image] =>[orig_patent_app_number] => 09769425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769425
Semiconductor memory circuit including a data output circuit Jan 25, 2001 Issued
Array ( [id] => 5950021 [patent_doc_number] => 20020006049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/769424 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7965 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006049.pdf [firstpage_image] =>[orig_patent_app_number] => 09769424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769424
Semiconductor memory device Jan 25, 2001 Issued
Array ( [id] => 7040536 [patent_doc_number] => 20010005336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Semiconductor memory having an overlaid bus structure' [patent_app_type] => new-utility [patent_app_number] => 09/771171 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14235 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005336.pdf [firstpage_image] =>[orig_patent_app_number] => 09771171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771171
Semiconductor memory having an overlaid bus structure Jan 25, 2001 Issued
Array ( [id] => 6891647 [patent_doc_number] => 20010017809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Circuit configuration having a variable number of data outputs and device for reading out data from the circuit configuration with the variable number of data outputs' [patent_app_type] => new [patent_app_number] => 09/766321 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5885 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017809.pdf [firstpage_image] =>[orig_patent_app_number] => 09766321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766321
Circuit configuration having a variable number of data outputs and device for reading out data from the circuit configuration with the variable number of data outputs Jan 18, 2001 Issued
Array ( [id] => 1550243 [patent_doc_number] => 06445615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-03 [patent_title] => 'Non-volatile semiconductor memory device and semiconductor disk device' [patent_app_type] => B2 [patent_app_number] => 09/758221 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 9164 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445615.pdf [firstpage_image] =>[orig_patent_app_number] => 09758221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758221
Non-volatile semiconductor memory device and semiconductor disk device Jan 11, 2001 Issued
Array ( [id] => 1480142 [patent_doc_number] => 06345011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-05 [patent_title] => 'Input/output line structure of a semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/758526 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3929 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345011.pdf [firstpage_image] =>[orig_patent_app_number] => 09758526 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758526
Input/output line structure of a semiconductor memory device Jan 9, 2001 Issued
Array ( [id] => 6902083 [patent_doc_number] => 20010000992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-10 [patent_title] => 'Methods for forming and programming aligned fuses disposed in an integrated circuit' [patent_app_type] => new-utility [patent_app_number] => 09/755848 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5745 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000992.pdf [firstpage_image] =>[orig_patent_app_number] => 09755848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755848
Methods for forming and programming aligned fuses disposed in an integrated circuit Jan 4, 2001 Issued
Array ( [id] => 6882139 [patent_doc_number] => 20010048611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Method and system for validating flash memory' [patent_app_type] => new [patent_app_number] => 09/755328 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048611.pdf [firstpage_image] =>[orig_patent_app_number] => 09755328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755328
Method and system for validating flash memory Jan 4, 2001 Issued
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