Huan Hoang

Array ( [id] => 1410441 [patent_doc_number] => 06545921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor memory device allowing spare memory cell to be tested efficiently' [patent_app_type] => B2 [patent_app_number] => 09/754123 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8875 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545921.pdf [firstpage_image] =>[orig_patent_app_number] => 09754123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1599790 [patent_doc_number] => 06385121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-07 [patent_title] => 'Semiconductor memory device having a plurality of banks sharing a column control unit' [patent_app_type] => B2 [patent_app_number] => 09/750228 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2898 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385121.pdf [firstpage_image] =>[orig_patent_app_number] => 09750228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1600025 [patent_doc_number] => 06493250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Multi-tier point-to-point buffered memory interface' [patent_app_type] => B2 [patent_app_number] => 09/753024 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6057 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493250.pdf [firstpage_image] =>[orig_patent_app_number] => 09753024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4329579 [patent_doc_number] => 06331949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Circuit for storing and latching defective address data for a nonvolatile semiconductor memory device having redundant function' [patent_app_type] => 1 [patent_app_number] => 9/745526 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 13258 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331949.pdf [firstpage_image] =>[orig_patent_app_number] => 745526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1480114 [patent_doc_number] => 06345004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Repair analysis circuit for redundancy, redundant repairing method, and semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/745421 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5784 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345004.pdf [firstpage_image] =>[orig_patent_app_number] => 09745421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565273 [patent_doc_number] => 06363031 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/747790 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1422 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363031.pdf [firstpage_image] =>[orig_patent_app_number] => 09747790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1470073 [patent_doc_number] => 06459646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Bank-based configuration and reconfiguration for programmable logic in a system on a chip' [patent_app_type] => B1 [patent_app_number] => 09/746524 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2427 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459646.pdf [firstpage_image] =>[orig_patent_app_number] => 09746524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7642957 [patent_doc_number] => 06430089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/740959 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6750 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430089.pdf [firstpage_image] =>[orig_patent_app_number] => 09740959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478446 [patent_doc_number] => 06388919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Memory controller for flash memory system and method for writing data to flash memory device' [patent_app_type] => B2 [patent_app_number] => 09/741228 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14497 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388919.pdf [firstpage_image] =>[orig_patent_app_number] => 09741228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1555191 [patent_doc_number] => 06400640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method for memory addressing' [patent_app_type] => B2 [patent_app_number] => 09/738324 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1925 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400640.pdf [firstpage_image] =>[orig_patent_app_number] => 09738324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1525660 [patent_doc_number] => 06353572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-05 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/736124 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5993 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353572.pdf [firstpage_image] =>[orig_patent_app_number] => 09736124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6902085 [patent_doc_number] => 20010000994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-10 [patent_title] => 'Semiconductor device reconciling different timing signals' [patent_app_type] => new-utility [patent_app_number] => 09/733961 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 16405 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000994.pdf [firstpage_image] =>[orig_patent_app_number] => 09733961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7077848 [patent_doc_number] => 20010040817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'SRAM having a reduced chip area' [patent_app_type] => new [patent_app_number] => 09/734029 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2587 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040817.pdf [firstpage_image] =>[orig_patent_app_number] => 09734029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1443060 [patent_doc_number] => 06335900 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method and apparatus for selectable wordline boosting in a memory device' [patent_app_type] => B1 [patent_app_number] => 09/734226 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335900.pdf [firstpage_image] =>[orig_patent_app_number] => 09734226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7040531 [patent_doc_number] => 20010005331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Dual-to -single-rail converter for the read out of static storage arrays' [patent_app_type] => new-utility [patent_app_number] => 09/733328 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2878 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005331.pdf [firstpage_image] =>[orig_patent_app_number] => 09733328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1488596 [patent_doc_number] => 06366508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Integrated circuit memory having column redundancy with no timing penalty' [patent_app_type] => B1 [patent_app_number] => 09/729020 [patent_app_country] => US [patent_app_date] => 2000-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6129 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366508.pdf [firstpage_image] =>[orig_patent_app_number] => 09729020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1442980 [patent_doc_number] => 06335877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Driving circuit of nonvolatile ferroelectric memory device and method for driving the same' [patent_app_type] => B1 [patent_app_number] => 09/722827 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4878 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335877.pdf [firstpage_image] =>[orig_patent_app_number] => 09722827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419536 [patent_doc_number] => 06301191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor memory device allowing reduction in power consumption during standby' [patent_app_type] => 1 [patent_app_number] => 9/723227 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 52 [patent_no_of_words] => 22908 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301191.pdf [firstpage_image] =>[orig_patent_app_number] => 723227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644614 [patent_doc_number] => 06473359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/722043 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6408 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473359.pdf [firstpage_image] =>[orig_patent_app_number] => 09722043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4418522 [patent_doc_number] => 06310806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Semiconductor memory device with redundant circuit' [patent_app_type] => 1 [patent_app_number] => 9/716322 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 33 [patent_no_of_words] => 17494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310806.pdf [firstpage_image] =>[orig_patent_app_number] => 716322 [rel_patent_id] =>[rel_patent_doc_number] =>)