Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1437674 [patent_doc_number] => 06356482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure' [patent_app_type] => B1 [patent_app_number] => 09/657029 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5147 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356482.pdf [firstpage_image] =>[orig_patent_app_number] => 09657029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657029
Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure Sep 6, 2000 Issued
Array ( [id] => 4384121 [patent_doc_number] => 06288934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Analog memory device and method for reading data stored therein' [patent_app_type] => 1 [patent_app_number] => 9/656028 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5617 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288934.pdf [firstpage_image] =>[orig_patent_app_number] => 656028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656028
Analog memory device and method for reading data stored therein Sep 5, 2000 Issued
Array ( [id] => 1565057 [patent_doc_number] => 06362991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Miss detector' [patent_app_type] => B1 [patent_app_number] => 09/654720 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1484 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362991.pdf [firstpage_image] =>[orig_patent_app_number] => 09654720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654720
Miss detector Sep 4, 2000 Issued
Array ( [id] => 4317441 [patent_doc_number] => 06327166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/651322 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8133 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327166.pdf [firstpage_image] =>[orig_patent_app_number] => 651322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651322
Semiconductor device Aug 30, 2000 Issued
Array ( [id] => 1564200 [patent_doc_number] => 06438023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Double-edged clocked storage device and method' [patent_app_type] => B1 [patent_app_number] => 09/652622 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4861 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438023.pdf [firstpage_image] =>[orig_patent_app_number] => 09652622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652622
Double-edged clocked storage device and method Aug 30, 2000 Issued
Array ( [id] => 1567582 [patent_doc_number] => 06339539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Content addressable memory having read/write capabilities that do not interrupt continuous search cycles' [patent_app_type] => B1 [patent_app_number] => 09/651426 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 7890 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339539.pdf [firstpage_image] =>[orig_patent_app_number] => 09651426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651426
Content addressable memory having read/write capabilities that do not interrupt continuous search cycles Aug 29, 2000 Issued
Array ( [id] => 4418549 [patent_doc_number] => 06310809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Adjustable pre-charge in a memory' [patent_app_type] => 1 [patent_app_number] => 9/648722 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7251 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310809.pdf [firstpage_image] =>[orig_patent_app_number] => 648722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648722
Adjustable pre-charge in a memory Aug 24, 2000 Issued
Array ( [id] => 4416211 [patent_doc_number] => 06272037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Ferroelectric memory device and method for generating reference level signal therefor' [patent_app_type] => 1 [patent_app_number] => 9/645720 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8809 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272037.pdf [firstpage_image] =>[orig_patent_app_number] => 645720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645720
Ferroelectric memory device and method for generating reference level signal therefor Aug 23, 2000 Issued
Array ( [id] => 7642951 [patent_doc_number] => 06430095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method for cell margin testing a dynamic cell plate sensing memory architecture' [patent_app_type] => B1 [patent_app_number] => 09/644497 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2312 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430095.pdf [firstpage_image] =>[orig_patent_app_number] => 09644497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644497
Method for cell margin testing a dynamic cell plate sensing memory architecture Aug 22, 2000 Issued
Array ( [id] => 1480118 [patent_doc_number] => 06345006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Memory circuit with local isolation and pre-charge circuits' [patent_app_type] => B1 [patent_app_number] => 09/642089 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5515 [patent_no_of_claims] => 110 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345006.pdf [firstpage_image] =>[orig_patent_app_number] => 09642089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642089
Memory circuit with local isolation and pre-charge circuits Aug 20, 2000 Issued
Array ( [id] => 4374229 [patent_doc_number] => 06256251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Circuit with variable voltage boosting ratios in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/638022 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1802 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256251.pdf [firstpage_image] =>[orig_patent_app_number] => 638022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638022
Circuit with variable voltage boosting ratios in a memory device Aug 13, 2000 Issued
09/638428 Low-cost three-dimensional memory array Aug 13, 2000 Abandoned
Array ( [id] => 4419276 [patent_doc_number] => 06301167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Apparatus for testing semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/638385 [patent_app_country] => US [patent_app_date] => 2000-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2549 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301167.pdf [firstpage_image] =>[orig_patent_app_number] => 638385 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638385
Apparatus for testing semiconductor memory Aug 11, 2000 Issued
Array ( [id] => 4383868 [patent_doc_number] => 06288922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Structure and method of an encoded ternary content addressable memory (CAM) cell for low-power compare operation' [patent_app_type] => 1 [patent_app_number] => 9/637124 [patent_app_country] => US [patent_app_date] => 2000-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2066 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288922.pdf [firstpage_image] =>[orig_patent_app_number] => 637124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/637124
Structure and method of an encoded ternary content addressable memory (CAM) cell for low-power compare operation Aug 10, 2000 Issued
Array ( [id] => 4419989 [patent_doc_number] => 06229735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Burst read mode word line boosting' [patent_app_type] => 1 [patent_app_number] => 9/638055 [patent_app_country] => US [patent_app_date] => 2000-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4513 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229735.pdf [firstpage_image] =>[orig_patent_app_number] => 638055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638055
Burst read mode word line boosting Aug 10, 2000 Issued
Array ( [id] => 4420049 [patent_doc_number] => 06266278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Dual floating gate EEPROM cell array with steering gates shared adjacent cells' [patent_app_type] => 1 [patent_app_number] => 9/634694 [patent_app_country] => US [patent_app_date] => 2000-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9521 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266278.pdf [firstpage_image] =>[orig_patent_app_number] => 634694 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/634694
Dual floating gate EEPROM cell array with steering gates shared adjacent cells Aug 7, 2000 Issued
Array ( [id] => 4341885 [patent_doc_number] => 06320792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method' [patent_app_type] => 1 [patent_app_number] => 9/633334 [patent_app_country] => US [patent_app_date] => 2000-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4111 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320792.pdf [firstpage_image] =>[orig_patent_app_number] => 633334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/633334
Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method Aug 6, 2000 Issued
Array ( [id] => 4384250 [patent_doc_number] => 06288942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Nonvolatile semiconductor storage device and its manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/632626 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 4483 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288942.pdf [firstpage_image] =>[orig_patent_app_number] => 632626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632626
Nonvolatile semiconductor storage device and its manufacturing method Aug 3, 2000 Issued
Array ( [id] => 1488656 [patent_doc_number] => 06366524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Address decoding in multiple-bank memory architectures' [patent_app_type] => B1 [patent_app_number] => 09/628197 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5525 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366524.pdf [firstpage_image] =>[orig_patent_app_number] => 09628197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628197
Address decoding in multiple-bank memory architectures Jul 27, 2000 Issued
Array ( [id] => 1565184 [patent_doc_number] => 06363011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Semiconductor non-volatile latch device including non-volatile elements' [patent_app_type] => B1 [patent_app_number] => 09/626267 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 21456 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363011.pdf [firstpage_image] =>[orig_patent_app_number] => 09626267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626267
Semiconductor non-volatile latch device including non-volatile elements Jul 24, 2000 Issued
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