Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4290913 [patent_doc_number] => 06282119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Mixed program and sense architecture using dual-step voltage scheme in multi-level data storage in flash memories' [patent_app_type] => 1 [patent_app_number] => 9/585422 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282119.pdf [firstpage_image] =>[orig_patent_app_number] => 585422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585422
Mixed program and sense architecture using dual-step voltage scheme in multi-level data storage in flash memories Jun 1, 2000 Issued
Array ( [id] => 4425550 [patent_doc_number] => 06195284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/579320 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8289 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195284.pdf [firstpage_image] =>[orig_patent_app_number] => 579320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/579320
Semiconductor memory device May 24, 2000 Issued
Array ( [id] => 1565211 [patent_doc_number] => 06363018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Methods and apparatus for reading memory device register data' [patent_app_type] => B1 [patent_app_number] => 09/571028 [patent_app_country] => US [patent_app_date] => 2000-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363018.pdf [firstpage_image] =>[orig_patent_app_number] => 09571028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571028
Methods and apparatus for reading memory device register data May 14, 2000 Issued
Array ( [id] => 1488632 [patent_doc_number] => 06366518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Circuit configuration for programming an electrically programmable element' [patent_app_type] => B1 [patent_app_number] => 09/571486 [patent_app_country] => US [patent_app_date] => 2000-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2452 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366518.pdf [firstpage_image] =>[orig_patent_app_number] => 09571486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571486
Circuit configuration for programming an electrically programmable element May 14, 2000 Issued
Array ( [id] => 4396695 [patent_doc_number] => 06262921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Delay-locked loop with binary-coupled capacitor' [patent_app_type] => 1 [patent_app_number] => 9/570241 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7250 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262921.pdf [firstpage_image] =>[orig_patent_app_number] => 570241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570241
Delay-locked loop with binary-coupled capacitor May 11, 2000 Issued
Array ( [id] => 4374336 [patent_doc_number] => 06256259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Delay-locked loop with binary-coupled capacitor' [patent_app_type] => 1 [patent_app_number] => 9/570242 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7252 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256259.pdf [firstpage_image] =>[orig_patent_app_number] => 570242 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570242
Delay-locked loop with binary-coupled capacitor May 11, 2000 Issued
Array ( [id] => 4416428 [patent_doc_number] => 06272060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Shift register clock scheme' [patent_app_type] => 1 [patent_app_number] => 9/569820 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4743 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272060.pdf [firstpage_image] =>[orig_patent_app_number] => 569820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569820
Shift register clock scheme May 11, 2000 Issued
Array ( [id] => 1555067 [patent_doc_number] => 06400603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Electronically-eraseable programmable read-only memory having reduced-page-size program and erase' [patent_app_type] => B1 [patent_app_number] => 09/564324 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7874 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400603.pdf [firstpage_image] =>[orig_patent_app_number] => 09564324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564324
Electronically-eraseable programmable read-only memory having reduced-page-size program and erase May 2, 2000 Issued
Array ( [id] => 1499245 [patent_doc_number] => 06404687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor integrated circuit having a self-refresh function' [patent_app_type] => B2 [patent_app_number] => 09/562925 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 5529 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404687.pdf [firstpage_image] =>[orig_patent_app_number] => 09562925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562925
Semiconductor integrated circuit having a self-refresh function May 1, 2000 Issued
Array ( [id] => 1585435 [patent_doc_number] => 06424585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Semiconductor memory device with a voltage down converter stably generating an internal down-converted voltage' [patent_app_type] => B1 [patent_app_number] => 09/561816 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 95 [patent_figures_cnt] => 147 [patent_no_of_words] => 83275 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424585.pdf [firstpage_image] =>[orig_patent_app_number] => 09561816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561816
Semiconductor memory device with a voltage down converter stably generating an internal down-converted voltage Apr 30, 2000 Issued
Array ( [id] => 4273148 [patent_doc_number] => 06205086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Phase control circuit, semiconductor device and semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/560724 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 12959 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205086.pdf [firstpage_image] =>[orig_patent_app_number] => 560724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/560724
Phase control circuit, semiconductor device and semiconductor memory Apr 27, 2000 Issued
Array ( [id] => 4273501 [patent_doc_number] => 06259645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Matching loading between sensing reference and memory cell with reduced transistor count in a dual-bank flash memory' [patent_app_type] => 1 [patent_app_number] => 9/557728 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4847 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259645.pdf [firstpage_image] =>[orig_patent_app_number] => 557728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/557728
Matching loading between sensing reference and memory cell with reduced transistor count in a dual-bank flash memory Apr 25, 2000 Issued
Array ( [id] => 4366643 [patent_doc_number] => 06292383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Redundant memory cell for dynamic random access memories having twisted bit line architectures' [patent_app_type] => 1 [patent_app_number] => 9/559028 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3387 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292383.pdf [firstpage_image] =>[orig_patent_app_number] => 559028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559028
Redundant memory cell for dynamic random access memories having twisted bit line architectures Apr 24, 2000 Issued
Array ( [id] => 4291012 [patent_doc_number] => 06282125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method for erasing and rewriting non volatile memory cells and particularly flash cells' [patent_app_type] => 1 [patent_app_number] => 9/553526 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2677 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282125.pdf [firstpage_image] =>[orig_patent_app_number] => 553526 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/553526
Method for erasing and rewriting non volatile memory cells and particularly flash cells Apr 19, 2000 Issued
Array ( [id] => 4393884 [patent_doc_number] => 06295236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Semiconductor memory of the random access type with a bus system organized in two planes' [patent_app_type] => 1 [patent_app_number] => 9/553128 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2568 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295236.pdf [firstpage_image] =>[orig_patent_app_number] => 553128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/553128
Semiconductor memory of the random access type with a bus system organized in two planes Apr 18, 2000 Issued
Array ( [id] => 4425548 [patent_doc_number] => 06178116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Memory cell of non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/550791 [patent_app_country] => US [patent_app_date] => 2000-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 13545 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178116.pdf [firstpage_image] =>[orig_patent_app_number] => 550791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/550791
Memory cell of non-volatile semiconductor memory device Apr 16, 2000 Issued
Array ( [id] => 4317987 [patent_doc_number] => 06252796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Device comprising a first and a second ferromagnetic layer separated by a non-magnetic spacer layer' [patent_app_type] => 1 [patent_app_number] => 9/529524 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2623 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252796.pdf [firstpage_image] =>[orig_patent_app_number] => 529524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/529524
Device comprising a first and a second ferromagnetic layer separated by a non-magnetic spacer layer Apr 12, 2000 Issued
Array ( [id] => 4309965 [patent_doc_number] => 06185151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Synchronous memory device with programmable write cycle and data write method using the same' [patent_app_type] => 1 [patent_app_number] => 9/548220 [patent_app_country] => US [patent_app_date] => 2000-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6888 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185151.pdf [firstpage_image] =>[orig_patent_app_number] => 548220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/548220
Synchronous memory device with programmable write cycle and data write method using the same Apr 11, 2000 Issued
Array ( [id] => 4418803 [patent_doc_number] => 06240024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method and apparatus for generating an echo clock in a memory' [patent_app_type] => 1 [patent_app_number] => 9/546022 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240024.pdf [firstpage_image] =>[orig_patent_app_number] => 546022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/546022
Method and apparatus for generating an echo clock in a memory Apr 9, 2000 Issued
Array ( [id] => 1589966 [patent_doc_number] => 06359810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Page mode erase in a flash memory array' [patent_app_type] => B1 [patent_app_number] => 09/542434 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4667 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359810.pdf [firstpage_image] =>[orig_patent_app_number] => 09542434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542434
Page mode erase in a flash memory array Apr 3, 2000 Issued
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