Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1478425 [patent_doc_number] => 06388912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Quantum magnetic memory' [patent_app_type] => B1 [patent_app_number] => 09/539722 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6650 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388912.pdf [firstpage_image] =>[orig_patent_app_number] => 09539722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539722
Quantum magnetic memory Mar 29, 2000 Issued
Array ( [id] => 4374084 [patent_doc_number] => 06256241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Short write test mode for testing static memory cells' [patent_app_type] => 1 [patent_app_number] => 9/539222 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256241.pdf [firstpage_image] =>[orig_patent_app_number] => 539222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539222
Short write test mode for testing static memory cells Mar 29, 2000 Issued
Array ( [id] => 4367054 [patent_doc_number] => 06292411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Delay control circuit synchronous with clock signal' [patent_app_type] => 1 [patent_app_number] => 9/537424 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 10850 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292411.pdf [firstpage_image] =>[orig_patent_app_number] => 537424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537424
Delay control circuit synchronous with clock signal Mar 26, 2000 Issued
Array ( [id] => 4341685 [patent_doc_number] => 06320777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Dynamic content addressable memory cell' [patent_app_type] => 1 [patent_app_number] => 9/533128 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6272 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320777.pdf [firstpage_image] =>[orig_patent_app_number] => 533128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533128
Dynamic content addressable memory cell Mar 22, 2000 Issued
Array ( [id] => 4342038 [patent_doc_number] => 06320803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/533226 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4650 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320803.pdf [firstpage_image] =>[orig_patent_app_number] => 533226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533226
Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits Mar 22, 2000 Issued
Array ( [id] => 6960447 [patent_doc_number] => 20010012216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Semiconductor memory device for effecting erasing operation in block unit' [patent_app_type] => new [patent_app_number] => 09/532824 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9720 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012216.pdf [firstpage_image] =>[orig_patent_app_number] => 09532824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532824
Semiconductor memory device for effecting erasing operation in block unit Mar 20, 2000 Issued
Array ( [id] => 4096081 [patent_doc_number] => 06163502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Clocking to support interface of memory controller to external SRAM' [patent_app_type] => 1 [patent_app_number] => 9/527622 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2429 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163502.pdf [firstpage_image] =>[orig_patent_app_number] => 527622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527622
Clocking to support interface of memory controller to external SRAM Mar 16, 2000 Issued
Array ( [id] => 4372438 [patent_doc_number] => 06191985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Dynamic memory having two modes of operation' [patent_app_type] => 1 [patent_app_number] => 9/528424 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4335 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191985.pdf [firstpage_image] =>[orig_patent_app_number] => 528424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/528424
Dynamic memory having two modes of operation Mar 16, 2000 Issued
Array ( [id] => 4369604 [patent_doc_number] => 06219295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor memory with transfer buffer structure' [patent_app_type] => 1 [patent_app_number] => 9/526349 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 13525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219295.pdf [firstpage_image] =>[orig_patent_app_number] => 526349 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/526349
Semiconductor memory with transfer buffer structure Mar 15, 2000 Issued
Array ( [id] => 1442970 [patent_doc_number] => 06335873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/525226 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 155 [patent_no_of_words] => 21855 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335873.pdf [firstpage_image] =>[orig_patent_app_number] => 09525226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/525226
Semiconductor integrated circuit device Mar 13, 2000 Issued
Array ( [id] => 4096066 [patent_doc_number] => 06163501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/520720 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5048 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163501.pdf [firstpage_image] =>[orig_patent_app_number] => 520720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520720
Synchronous semiconductor memory device Mar 7, 2000 Issued
Array ( [id] => 4309175 [patent_doc_number] => 06198666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Control input timing-independent dynamic multiplexer circuit' [patent_app_type] => 1 [patent_app_number] => 9/515526 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1914 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198666.pdf [firstpage_image] =>[orig_patent_app_number] => 515526 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515526
Control input timing-independent dynamic multiplexer circuit Feb 28, 2000 Issued
Array ( [id] => 4418598 [patent_doc_number] => 06240005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Sense amplifier configuration with fused diffusion regions and a distributed driver system' [patent_app_type] => 1 [patent_app_number] => 9/511820 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1943 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240005.pdf [firstpage_image] =>[orig_patent_app_number] => 511820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511820
Sense amplifier configuration with fused diffusion regions and a distributed driver system Feb 23, 2000 Issued
Array ( [id] => 4298621 [patent_doc_number] => 06269037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Variable equilibrate voltage circuit for paired digit lines' [patent_app_type] => 1 [patent_app_number] => 9/511520 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3708 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269037.pdf [firstpage_image] =>[orig_patent_app_number] => 511520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511520
Variable equilibrate voltage circuit for paired digit lines Feb 22, 2000 Issued
Array ( [id] => 4420148 [patent_doc_number] => 06266287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Variable equilibrate voltage circuit for paired digit lines' [patent_app_type] => 1 [patent_app_number] => 9/511471 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266287.pdf [firstpage_image] =>[orig_patent_app_number] => 511471 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511471
Variable equilibrate voltage circuit for paired digit lines Feb 22, 2000 Issued
Array ( [id] => 1461171 [patent_doc_number] => 06426908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Semiconductor memory device with reduced current consumption in data hold mode' [patent_app_type] => B1 [patent_app_number] => 09/511927 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 64 [patent_no_of_words] => 26520 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426908.pdf [firstpage_image] =>[orig_patent_app_number] => 09511927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511927
Semiconductor memory device with reduced current consumption in data hold mode Feb 22, 2000 Issued
Array ( [id] => 4416983 [patent_doc_number] => 06233191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Field programmable memory array' [patent_app_type] => 1 [patent_app_number] => 9/510326 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 67 [patent_no_of_words] => 24696 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233191.pdf [firstpage_image] =>[orig_patent_app_number] => 510326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510326
Field programmable memory array Feb 21, 2000 Issued
Array ( [id] => 4331290 [patent_doc_number] => 06249465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Redundancy programming using addressable scan paths to reduce the number of required fuses' [patent_app_type] => 1 [patent_app_number] => 9/506620 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249465.pdf [firstpage_image] =>[orig_patent_app_number] => 506620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506620
Redundancy programming using addressable scan paths to reduce the number of required fuses Feb 17, 2000 Issued
Array ( [id] => 4373776 [patent_doc_number] => 06256221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines' [patent_app_type] => 1 [patent_app_number] => 9/507106 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 8591 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256221.pdf [firstpage_image] =>[orig_patent_app_number] => 507106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507106
Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines Feb 16, 2000 Issued
Array ( [id] => 1567635 [patent_doc_number] => 06339549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Semiconductor storage apparatus having main bit line and sub bit line' [patent_app_type] => B1 [patent_app_number] => 09/501624 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6365 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339549.pdf [firstpage_image] =>[orig_patent_app_number] => 09501624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501624
Semiconductor storage apparatus having main bit line and sub bit line Feb 8, 2000 Issued
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