
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4250682
[patent_doc_number] => 06144602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/493624
[patent_app_country] => US
[patent_app_date] => 2000-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3710
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144602.pdf
[firstpage_image] =>[orig_patent_app_number] => 493624
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/493624 | Semiconductor memory device | Jan 27, 2000 | Issued |
Array
(
[id] => 1525605
[patent_doc_number] => 06353549
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-05
[patent_title] => 'Architecture and package orientation for high speed memory devices'
[patent_app_type] => B1
[patent_app_number] => 09/492412
[patent_app_country] => US
[patent_app_date] => 2000-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5479
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/353/06353549.pdf
[firstpage_image] =>[orig_patent_app_number] => 09492412
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/492412 | Architecture and package orientation for high speed memory devices | Jan 26, 2000 | Issued |
Array
(
[id] => 4425618
[patent_doc_number] => 06195302
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Dual slope sense clock generator'
[patent_app_type] => 1
[patent_app_number] => 9/492726
[patent_app_country] => US
[patent_app_date] => 2000-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4536
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/195/06195302.pdf
[firstpage_image] =>[orig_patent_app_number] => 492726
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/492726 | Dual slope sense clock generator | Jan 26, 2000 | Issued |
Array
(
[id] => 4273235
[patent_doc_number] => 06259627
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Read and write operations using constant row line voltage and variable column line load'
[patent_app_type] => 1
[patent_app_number] => 9/493026
[patent_app_country] => US
[patent_app_date] => 2000-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 10296
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/259/06259627.pdf
[firstpage_image] =>[orig_patent_app_number] => 493026
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/493026 | Read and write operations using constant row line voltage and variable column line load | Jan 26, 2000 | Issued |
Array
(
[id] => 4147744
[patent_doc_number] => 06122194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Semiconductor memory device with a column redundancy occupying a less chip area'
[patent_app_type] => 1
[patent_app_number] => 9/491846
[patent_app_country] => US
[patent_app_date] => 2000-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 6471
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/122/06122194.pdf
[firstpage_image] =>[orig_patent_app_number] => 491846
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/491846 | Semiconductor memory device with a column redundancy occupying a less chip area | Jan 25, 2000 | Issued |
Array
(
[id] => 1413694
[patent_doc_number] => 06542413
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'Multiple access storage device'
[patent_app_type] => B1
[patent_app_number] => 09/491428
[patent_app_country] => US
[patent_app_date] => 2000-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6721
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/542/06542413.pdf
[firstpage_image] =>[orig_patent_app_number] => 09491428
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/491428 | Multiple access storage device | Jan 25, 2000 | Issued |
Array
(
[id] => 1450075
[patent_doc_number] => 06370080
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-04-09
[patent_title] => 'Semiconductor memory for logic-hybrid memory'
[patent_app_type] => B2
[patent_app_number] => 09/477032
[patent_app_country] => US
[patent_app_date] => 2000-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 4058
[patent_no_of_claims] => 81
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/370/06370080.pdf
[firstpage_image] =>[orig_patent_app_number] => 09477032
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/477032 | Semiconductor memory for logic-hybrid memory | Jan 2, 2000 | Issued |
Array
(
[id] => 4327656
[patent_doc_number] => 06243315
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Computer memory system with a low power down mode'
[patent_app_type] => 1
[patent_app_number] => 9/477920
[patent_app_country] => US
[patent_app_date] => 1999-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 59
[patent_figures_cnt] => 67
[patent_no_of_words] => 7639
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/243/06243315.pdf
[firstpage_image] =>[orig_patent_app_number] => 477920
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/477920 | Computer memory system with a low power down mode | Dec 30, 1999 | Issued |
Array
(
[id] => 4169758
[patent_doc_number] => 06108231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Solid state director for beams'
[patent_app_type] => 1
[patent_app_number] => 9/475478
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6415
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/108/06108231.pdf
[firstpage_image] =>[orig_patent_app_number] => 475478
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475478 | Solid state director for beams | Dec 29, 1999 | Issued |
Array
(
[id] => 4309537
[patent_doc_number] => 06181636
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Output line arrangement structure of row decoding array'
[patent_app_type] => 1
[patent_app_number] => 9/475026
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1803
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/181/06181636.pdf
[firstpage_image] =>[orig_patent_app_number] => 475026
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475026 | Output line arrangement structure of row decoding array | Dec 29, 1999 | Issued |
Array
(
[id] => 4185696
[patent_doc_number] => 06141280
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Refresh period automatic detecting device for semiconductor memory device, method of automatically detecting refresh period, and refresh period output device'
[patent_app_type] => 1
[patent_app_number] => 9/474128
[patent_app_country] => US
[patent_app_date] => 1999-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4007
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/141/06141280.pdf
[firstpage_image] =>[orig_patent_app_number] => 474128
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/474128 | Refresh period automatic detecting device for semiconductor memory device, method of automatically detecting refresh period, and refresh period output device | Dec 28, 1999 | Issued |
Array
(
[id] => 4393175
[patent_doc_number] => 06304486
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Sensing time control device and method'
[patent_app_type] => 1
[patent_app_number] => 9/468422
[patent_app_country] => US
[patent_app_date] => 1999-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6865
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/304/06304486.pdf
[firstpage_image] =>[orig_patent_app_number] => 468422
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/468422 | Sensing time control device and method | Dec 19, 1999 | Issued |
Array
(
[id] => 4425593
[patent_doc_number] => 06178135
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Multi-bank memory devices having bank selection switches therein that enable efficient sense amplifier utilization'
[patent_app_type] => 1
[patent_app_number] => 9/464826
[patent_app_country] => US
[patent_app_date] => 1999-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3943
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/178/06178135.pdf
[firstpage_image] =>[orig_patent_app_number] => 464826
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/464826 | Multi-bank memory devices having bank selection switches therein that enable efficient sense amplifier utilization | Dec 16, 1999 | Issued |
Array
(
[id] => 4417079
[patent_doc_number] => 06233200
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-15
[patent_title] => 'Method and apparatus for selectively disabling clock distribution'
[patent_app_type] => 1
[patent_app_number] => 9/465220
[patent_app_country] => US
[patent_app_date] => 1999-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1574
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/233/06233200.pdf
[firstpage_image] =>[orig_patent_app_number] => 465220
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/465220 | Method and apparatus for selectively disabling clock distribution | Dec 14, 1999 | Issued |
Array
(
[id] => 4393525
[patent_doc_number] => 06304509
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Semiconductor storage unit'
[patent_app_type] => 1
[patent_app_number] => 9/443624
[patent_app_country] => US
[patent_app_date] => 1999-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 35
[patent_no_of_words] => 26459
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/304/06304509.pdf
[firstpage_image] =>[orig_patent_app_number] => 443624
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/443624 | Semiconductor storage unit | Nov 18, 1999 | Issued |
Array
(
[id] => 4250261
[patent_doc_number] => 06144574
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Associative memory with a shortest mask output function and search method'
[patent_app_type] => 1
[patent_app_number] => 9/441122
[patent_app_country] => US
[patent_app_date] => 1999-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11593
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144574.pdf
[firstpage_image] =>[orig_patent_app_number] => 441122
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/441122 | Associative memory with a shortest mask output function and search method | Nov 16, 1999 | Issued |
Array
(
[id] => 4110553
[patent_doc_number] => 06067245
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'High speed, high bandwidth, high density nonvolatile memory system'
[patent_app_type] => 1
[patent_app_number] => 9/442355
[patent_app_country] => US
[patent_app_date] => 1999-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 3834
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/067/06067245.pdf
[firstpage_image] =>[orig_patent_app_number] => 442355
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/442355 | High speed, high bandwidth, high density nonvolatile memory system | Nov 16, 1999 | Issued |
Array
(
[id] => 4265998
[patent_doc_number] => 06208559
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb'
[patent_app_type] => 1
[patent_app_number] => 9/441220
[patent_app_country] => US
[patent_app_date] => 1999-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3886
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 396
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/208/06208559.pdf
[firstpage_image] =>[orig_patent_app_number] => 441220
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/441220 | Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb | Nov 14, 1999 | Issued |
Array
(
[id] => 4252624
[patent_doc_number] => 06166991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/433822
[patent_app_country] => US
[patent_app_date] => 1999-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1463
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/166/06166991.pdf
[firstpage_image] =>[orig_patent_app_number] => 433822
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/433822 | Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit | Nov 2, 1999 | Issued |
Array
(
[id] => 4247080
[patent_doc_number] => 06118689
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability'
[patent_app_type] => 1
[patent_app_number] => 9/427728
[patent_app_country] => US
[patent_app_date] => 1999-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2500
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/118/06118689.pdf
[firstpage_image] =>[orig_patent_app_number] => 427728
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/427728 | Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability | Oct 26, 1999 | Issued |