Huan Hoang

Array ( [id] => 7118171 [patent_doc_number] => 20010001597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE AND METHOD OF DRIVING THEREOF' [patent_app_type] => new-utility [patent_app_number] => 09/425196 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5476 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001597.pdf [firstpage_image] =>[orig_patent_app_number] => 09425196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309214 [patent_doc_number] => 06198669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/418985 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3396 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198669.pdf [firstpage_image] =>[orig_patent_app_number] => 418985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419133 [patent_doc_number] => 06301157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method and circuit for testing memory cells in a multilevel memory device' [patent_app_type] => 1 [patent_app_number] => 9/415024 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2282 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301157.pdf [firstpage_image] =>[orig_patent_app_number] => 415024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407052 [patent_doc_number] => 06297987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Magnetoresistive spin-injection diode' [patent_app_type] => 1 [patent_app_number] => 9/408526 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5821 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297987.pdf [firstpage_image] =>[orig_patent_app_number] => 408526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420129 [patent_doc_number] => 06229750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method and system for reducing power dissipation in a semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 9/408622 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4163 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229750.pdf [firstpage_image] =>[orig_patent_app_number] => 408622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139921 [patent_doc_number] => 06128208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/401185 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128208.pdf [firstpage_image] =>[orig_patent_app_number] => 401185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317339 [patent_doc_number] => 06188640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Data output circuits for semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/398828 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 18801 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188640.pdf [firstpage_image] =>[orig_patent_app_number] => 398828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4369206 [patent_doc_number] => 06169691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method for maintaining the memory content of non-volatile memory cells' [patent_app_type] => 1 [patent_app_number] => 9/397387 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169691.pdf [firstpage_image] =>[orig_patent_app_number] => 397387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170138 [patent_doc_number] => 06108256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'NFET/PFET RAM precharge circuitry to minimize read sense amp operational range' [patent_app_type] => 1 [patent_app_number] => 9/395922 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3620 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108256.pdf [firstpage_image] =>[orig_patent_app_number] => 395922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417278 [patent_doc_number] => 06172897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Semiconductor memory and write and read methods of the same' [patent_app_type] => 1 [patent_app_number] => 9/393183 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 5762 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172897.pdf [firstpage_image] =>[orig_patent_app_number] => 393183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170328 [patent_doc_number] => 06157576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/393301 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 82 [patent_no_of_words] => 39667 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157576.pdf [firstpage_image] =>[orig_patent_app_number] => 393301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419959 [patent_doc_number] => 06229732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices' [patent_app_type] => 1 [patent_app_number] => 9/380873 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4426 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229732.pdf [firstpage_image] =>[orig_patent_app_number] => 380873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326199 [patent_doc_number] => 06317360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Flash memory and methods of writing and erasing the same as well as a method of forming the same' [patent_app_type] => 1 [patent_app_number] => 9/387722 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 47 [patent_no_of_words] => 8659 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317360.pdf [firstpage_image] =>[orig_patent_app_number] => 387722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4369568 [patent_doc_number] => 06219293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and apparatus for supplying regulated power to memory device components' [patent_app_type] => 1 [patent_app_number] => 9/388126 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4381 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219293.pdf [firstpage_image] =>[orig_patent_app_number] => 388126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140469 [patent_doc_number] => 06128246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Semiconductor memory device having write recovery circuit structure' [patent_app_type] => 1 [patent_app_number] => 9/385140 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9448 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128246.pdf [firstpage_image] =>[orig_patent_app_number] => 385140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120671 [patent_doc_number] => 06058059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Sense/output circuit for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/385737 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3503 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 491 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058059.pdf [firstpage_image] =>[orig_patent_app_number] => 385737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197322 [patent_doc_number] => 06094389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Semiconductor memory apparatus having refresh test circuit' [patent_app_type] => 1 [patent_app_number] => 9/385436 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2610 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094389.pdf [firstpage_image] =>[orig_patent_app_number] => 385436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374070 [patent_doc_number] => 06256240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor memory circuit' [patent_app_type] => 1 [patent_app_number] => 9/385006 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4065 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256240.pdf [firstpage_image] =>[orig_patent_app_number] => 385006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110256 [patent_doc_number] => 06097635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Sensing circuit for programming/reading multilevel flash memory' [patent_app_type] => 1 [patent_app_number] => 9/379622 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4296 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097635.pdf [firstpage_image] =>[orig_patent_app_number] => 379622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4229723 [patent_doc_number] => 06111785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Nonvolatile semiconductor memory device capable of decreasing layout area for writing defective address' [patent_app_type] => 1 [patent_app_number] => 9/379009 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7995 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111785.pdf [firstpage_image] =>[orig_patent_app_number] => 379009 [rel_patent_id] =>[rel_patent_doc_number] =>)