Huan Hoang

Array ( [id] => 1358408 [patent_doc_number] => 06580639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Method of reducing program disturbs in NAND type flash memory devices' [patent_app_type] => B1 [patent_app_number] => 09/372406 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1500 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580639.pdf [firstpage_image] =>[orig_patent_app_number] => 09372406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4272552 [patent_doc_number] => 06205047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Data memory device having an exclusive-or function and method of reading data therefrom' [patent_app_type] => 1 [patent_app_number] => 9/369322 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 9233 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205047.pdf [firstpage_image] =>[orig_patent_app_number] => 369322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4095711 [patent_doc_number] => 06163477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'MRAM device using magnetic field bias to improve reproducibility of memory cell switching' [patent_app_type] => 1 [patent_app_number] => 9/370087 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3856 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163477.pdf [firstpage_image] =>[orig_patent_app_number] => 370087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252042 [patent_doc_number] => 06166951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Multi state sensing of NAND memory cells by applying reverse-bias voltage' [patent_app_type] => 1 [patent_app_number] => 9/370010 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1896 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166951.pdf [firstpage_image] =>[orig_patent_app_number] => 370010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252386 [patent_doc_number] => 06166973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Memory device with multiple-bit data pre-fetch function' [patent_app_type] => 1 [patent_app_number] => 9/365508 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 6856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166973.pdf [firstpage_image] =>[orig_patent_app_number] => 365508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185218 [patent_doc_number] => 06141248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'DRAM and SRAM memory cells with repressed memory' [patent_app_type] => 1 [patent_app_number] => 9/362909 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6062 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141248.pdf [firstpage_image] =>[orig_patent_app_number] => 362909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197067 [patent_doc_number] => 06094371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Memory device with ferroelectric capacitor' [patent_app_type] => 1 [patent_app_number] => 9/361609 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5693 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094371.pdf [firstpage_image] =>[orig_patent_app_number] => 361609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202177 [patent_doc_number] => 06130847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Semiconductor device with fast write recovery circuit' [patent_app_type] => 1 [patent_app_number] => 9/358339 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2188 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130847.pdf [firstpage_image] =>[orig_patent_app_number] => 358339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4418589 [patent_doc_number] => 06310813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Methods and apparatus for bypassing refreshing of selected portions of DRAM devices' [patent_app_type] => 1 [patent_app_number] => 9/358610 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4545 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310813.pdf [firstpage_image] =>[orig_patent_app_number] => 358610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202357 [patent_doc_number] => 06154404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Integrated circuit memory devices having sense amplifier driver circuits therein that improve writing efficiency' [patent_app_type] => 1 [patent_app_number] => 9/358138 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3756 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154404.pdf [firstpage_image] =>[orig_patent_app_number] => 358138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185517 [patent_doc_number] => 06141269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Semiconductor integrated circuit device using BiCMOS technology' [patent_app_type] => 1 [patent_app_number] => 9/357174 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 69 [patent_no_of_words] => 24657 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141269.pdf [firstpage_image] =>[orig_patent_app_number] => 357174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4115118 [patent_doc_number] => 06052323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Memory circuit including reduced area sense amplifier circuitry' [patent_app_type] => 1 [patent_app_number] => 9/354839 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 10612 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052323.pdf [firstpage_image] =>[orig_patent_app_number] => 354839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1555198 [patent_doc_number] => 06400641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Delay-locked loop with binary-coupled capacitor' [patent_app_type] => B1 [patent_app_number] => 09/353571 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7271 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400641.pdf [firstpage_image] =>[orig_patent_app_number] => 09353571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4284706 [patent_doc_number] => 06246604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Memory array architecture, method of operating a dynamic random access memory, and method of manufacturing a dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/353307 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3572 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246604.pdf [firstpage_image] =>[orig_patent_app_number] => 353307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197090 [patent_doc_number] => 06160742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Semiconductor memory device and data read method of device' [patent_app_type] => 1 [patent_app_number] => 9/353106 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8408 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160742.pdf [firstpage_image] =>[orig_patent_app_number] => 353106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247227 [patent_doc_number] => 06118699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Semiconductor memory device using MONOS type nonvolatile memory cell' [patent_app_type] => 1 [patent_app_number] => 9/352838 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 64 [patent_no_of_words] => 20280 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118699.pdf [firstpage_image] =>[orig_patent_app_number] => 352838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1523337 [patent_doc_number] => 06414876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Flash EEprom system' [patent_app_type] => B1 [patent_app_number] => 09/351829 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 37 [patent_no_of_words] => 19016 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414876.pdf [firstpage_image] =>[orig_patent_app_number] => 09351829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4093518 [patent_doc_number] => 06055193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Charge pump circuits and devices containing such' [patent_app_type] => 1 [patent_app_number] => 9/348808 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4355 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055193.pdf [firstpage_image] =>[orig_patent_app_number] => 348808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1306218 [patent_doc_number] => 06625064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Fast, low power, write scheme for memory circuits using pulsed off isolation device' [patent_app_type] => B1 [patent_app_number] => 09/819045 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6936 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625064.pdf [firstpage_image] =>[orig_patent_app_number] => 09819045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140497 [patent_doc_number] => 06128248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Semiconductor memory device including a clocking circuit for controlling the read circuit operation' [patent_app_type] => 1 [patent_app_number] => 9/345738 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 14038 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128248.pdf [firstpage_image] =>[orig_patent_app_number] => 345738 [rel_patent_id] =>[rel_patent_doc_number] =>)