Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7635493 [patent_doc_number] => 06381169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'High density non-volatile memory device' [patent_app_type] => B1 [patent_app_number] => 09/346228 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 33188 [patent_no_of_claims] => 93 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381169.pdf [firstpage_image] =>[orig_patent_app_number] => 09346228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346228
High density non-volatile memory device Jun 30, 1999 Issued
Array ( [id] => 4197707 [patent_doc_number] => 06151248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Dual floating gate EEPROM cell array with steering gates shared by adjacent cells' [patent_app_type] => 1 [patent_app_number] => 9/343328 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9521 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151248.pdf [firstpage_image] =>[orig_patent_app_number] => 343328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343328
Dual floating gate EEPROM cell array with steering gates shared by adjacent cells Jun 29, 1999 Issued
Array ( [id] => 4197578 [patent_doc_number] => 06151242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/343510 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 100 [patent_figures_cnt] => 232 [patent_no_of_words] => 53224 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151242.pdf [firstpage_image] =>[orig_patent_app_number] => 343510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343510
Semiconductor memory device Jun 29, 1999 Issued
Array ( [id] => 4117183 [patent_doc_number] => 06101141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Integrated memory' [patent_app_type] => 1 [patent_app_number] => 9/344922 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3377 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101141.pdf [firstpage_image] =>[orig_patent_app_number] => 344922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344922
Integrated memory Jun 27, 1999 Issued
Array ( [id] => 4252553 [patent_doc_number] => 06166986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/337010 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3026 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166986.pdf [firstpage_image] =>[orig_patent_app_number] => 337010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337010
Semiconductor memory device Jun 27, 1999 Issued
Array ( [id] => 4417655 [patent_doc_number] => 06172929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Integrated circuit having aligned fuses and methods for forming and programming the fuses' [patent_app_type] => 1 [patent_app_number] => 9/344436 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5735 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172929.pdf [firstpage_image] =>[orig_patent_app_number] => 344436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344436
Integrated circuit having aligned fuses and methods for forming and programming the fuses Jun 24, 1999 Issued
Array ( [id] => 4339170 [patent_doc_number] => 06313666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit' [patent_app_type] => 1 [patent_app_number] => 9/331780 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 11340 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313666.pdf [firstpage_image] =>[orig_patent_app_number] => 331780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/331780
Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit Jun 23, 1999 Issued
Array ( [id] => 4305344 [patent_doc_number] => 06236615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Semiconductor memory device having memory cell blocks different in data storage capacity without influence on peripheral circuits' [patent_app_type] => 1 [patent_app_number] => 9/334807 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6379 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236615.pdf [firstpage_image] =>[orig_patent_app_number] => 334807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334807
Semiconductor memory device having memory cell blocks different in data storage capacity without influence on peripheral circuits Jun 16, 1999 Issued
Array ( [id] => 4246064 [patent_doc_number] => 06075732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Semiconductor memory device with redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 9/334917 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 5200 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075732.pdf [firstpage_image] =>[orig_patent_app_number] => 334917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334917
Semiconductor memory device with redundancy circuit Jun 16, 1999 Issued
Array ( [id] => 4267905 [patent_doc_number] => 06259273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Programmable logic device with mixed mode programmable logic array' [patent_app_type] => 1 [patent_app_number] => 9/334149 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2452 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259273.pdf [firstpage_image] =>[orig_patent_app_number] => 334149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334149
Programmable logic device with mixed mode programmable logic array Jun 14, 1999 Issued
Array ( [id] => 4312399 [patent_doc_number] => 06252427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'CMOS inverter and standard cell using the same' [patent_app_type] => 1 [patent_app_number] => 9/333048 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252427.pdf [firstpage_image] =>[orig_patent_app_number] => 333048 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333048
CMOS inverter and standard cell using the same Jun 14, 1999 Issued
Array ( [id] => 4284769 [patent_doc_number] => 06281708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Tri-state bus amplifier-accelerator' [patent_app_type] => 1 [patent_app_number] => 9/333834 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2448 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281708.pdf [firstpage_image] =>[orig_patent_app_number] => 333834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333834
Tri-state bus amplifier-accelerator Jun 14, 1999 Issued
Array ( [id] => 6138585 [patent_doc_number] => 20020000833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'LOGIC GATE CELL' [patent_app_type] => new [patent_app_number] => 09/333456 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 11077 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000833.pdf [firstpage_image] =>[orig_patent_app_number] => 09333456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333456
Logic gate cell Jun 14, 1999 Issued
Array ( [id] => 4415865 [patent_doc_number] => 06229337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'High-density programmable logic device with flexible local connections and multiplexer based global interconnections' [patent_app_type] => 1 [patent_app_number] => 9/334143 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 9118 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229337.pdf [firstpage_image] =>[orig_patent_app_number] => 334143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334143
High-density programmable logic device with flexible local connections and multiplexer based global interconnections Jun 14, 1999 Issued
Array ( [id] => 4252611 [patent_doc_number] => 06166990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Clock reproduction circuit that can reproduce internal clock signal correctly in synchronization with external clock signal' [patent_app_type] => 1 [patent_app_number] => 9/332143 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 70 [patent_no_of_words] => 42402 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166990.pdf [firstpage_image] =>[orig_patent_app_number] => 332143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/332143
Clock reproduction circuit that can reproduce internal clock signal correctly in synchronization with external clock signal Jun 13, 1999 Issued
Array ( [id] => 4261556 [patent_doc_number] => 06137715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Static random access memory with rewriting circuit' [patent_app_type] => 1 [patent_app_number] => 9/328439 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4794 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137715.pdf [firstpage_image] =>[orig_patent_app_number] => 328439 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/328439
Static random access memory with rewriting circuit Jun 8, 1999 Issued
Array ( [id] => 4229638 [patent_doc_number] => 06111780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Radiation hardened six transistor random access memory and memory device' [patent_app_type] => 1 [patent_app_number] => 9/325645 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8876 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111780.pdf [firstpage_image] =>[orig_patent_app_number] => 325645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325645
Radiation hardened six transistor random access memory and memory device Jun 3, 1999 Issued
Array ( [id] => 4252113 [patent_doc_number] => 06091664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Elementary storage circuits' [patent_app_type] => 1 [patent_app_number] => 9/325139 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2602 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091664.pdf [firstpage_image] =>[orig_patent_app_number] => 325139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325139
Elementary storage circuits Jun 2, 1999 Issued
Array ( [id] => 1481396 [patent_doc_number] => 06389578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/318988 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8003 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389578.pdf [firstpage_image] =>[orig_patent_app_number] => 09318988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318988
Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit May 25, 1999 Issued
Array ( [id] => 1466521 [patent_doc_number] => 06393600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Skew-independent memory architecture' [patent_app_type] => B1 [patent_app_number] => 09/320191 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5214 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393600.pdf [firstpage_image] =>[orig_patent_app_number] => 09320191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320191
Skew-independent memory architecture May 25, 1999 Issued
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