Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17508788 [patent_doc_number] => 20220101891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => BIASING ELECTRONIC COMPONENTS USING ADJUSTABLE CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/546026 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546026
Biasing electronic components using adjustable circuitry Dec 7, 2021 Issued
Array ( [id] => 18688136 [patent_doc_number] => 11783879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Memory device comprising programmable command-and-address and/or data interfaces [patent_app_type] => utility [patent_app_number] => 17/531151 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 6413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531151
Memory device comprising programmable command-and-address and/or data interfaces Nov 18, 2021 Issued
Array ( [id] => 17463433 [patent_doc_number] => 20220076739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY CONTEXT RESTORE, REDUCTION OF BOOT TIME OF A SYSTEM ON A CHIP BY REDUCING DOUBLE DATA RATE MEMORY TRAINING [patent_app_type] => utility [patent_app_number] => 17/526429 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526429
Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training Nov 14, 2021 Issued
Array ( [id] => 18170462 [patent_doc_number] => 20230037073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => MEMORY DEVICE RELATED TO PERFORMING A COLUMN OPERATION [patent_app_type] => utility [patent_app_number] => 17/524307 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524307
Memory device related to performing a column operation Nov 10, 2021 Issued
Array ( [id] => 18593092 [patent_doc_number] => 11742000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Circuit module with improved line load [patent_app_type] => utility [patent_app_number] => 17/521894 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521894
Circuit module with improved line load Nov 8, 2021 Issued
Array ( [id] => 18347608 [patent_doc_number] => 20230135718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => REGULATOR CIRCUIT AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/518797 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518797
Regulator circuit and methods thereof Nov 3, 2021 Issued
Array ( [id] => 18645484 [patent_doc_number] => 11769562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Semiconductor device including an electronic fuse control circuit [patent_app_type] => utility [patent_app_number] => 17/517794 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7029 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517794
Semiconductor device including an electronic fuse control circuit Nov 2, 2021 Issued
Array ( [id] => 17431828 [patent_doc_number] => 20220059537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Semiconductor Memory Device Having an Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 17/517570 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517570
Semiconductor memory device having an electrically floating body transistor Nov 1, 2021 Issued
Array ( [id] => 17507307 [patent_doc_number] => 20220100410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CIRCUIT FOR TESTING A MEMORY AND TEST METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/510457 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510457 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510457
Circuit for testing a memory and test method thereof Oct 25, 2021 Issued
Array ( [id] => 18155915 [patent_doc_number] => 11568904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Memory with positively boosted write multiplexer [patent_app_type] => utility [patent_app_number] => 17/451110 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6584 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451110
Memory with positively boosted write multiplexer Oct 14, 2021 Issued
Array ( [id] => 18137093 [patent_doc_number] => 11562781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-24 [patent_title] => Memory devices with low pin count interfaces, and corresponding methods and systems [patent_app_type] => utility [patent_app_number] => 17/499938 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 54 [patent_no_of_words] => 11768 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499938
Memory devices with low pin count interfaces, and corresponding methods and systems Oct 12, 2021 Issued
Array ( [id] => 18548013 [patent_doc_number] => 11721371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Memory device having sense amplifier including plural sense circuits for sensing a voltage of a bit line in a read operation [patent_app_type] => utility [patent_app_number] => 17/495747 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 57 [patent_no_of_words] => 33445 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495747
Memory device having sense amplifier including plural sense circuits for sensing a voltage of a bit line in a read operation Oct 5, 2021 Issued
Array ( [id] => 18890845 [patent_doc_number] => 11869622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Memory with fine grain architectures [patent_app_type] => utility [patent_app_number] => 17/494606 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18812 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494606
Memory with fine grain architectures Oct 4, 2021 Issued
Array ( [id] => 17485662 [patent_doc_number] => 20220093166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => READ REFRESH OPERATION [patent_app_type] => utility [patent_app_number] => 17/488186 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488186
READ REFRESH OPERATION Sep 27, 2021 Abandoned
Array ( [id] => 17477056 [patent_doc_number] => 20220084560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => INTERCONNECTION FOR MEMORY ELECTRODES [patent_app_type] => utility [patent_app_number] => 17/484443 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484443
Interconnection for memory electrodes Sep 23, 2021 Issued
Array ( [id] => 18262917 [patent_doc_number] => 11610624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Memory device skipping refresh operation and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/474666 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 11847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474666 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474666
Memory device skipping refresh operation and operation method thereof Sep 13, 2021 Issued
Array ( [id] => 17373394 [patent_doc_number] => 20220028446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SENSE AMPLIFIER, MEMORY, AND METHOD FOR CONTROLLING SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/472792 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472792
Sense amplifier, memory, and method for controlling sense amplifier Sep 12, 2021 Issued
Array ( [id] => 18155912 [patent_doc_number] => 11568901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/470955 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5614 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470955
Semiconductor device Sep 8, 2021 Issued
Array ( [id] => 17691885 [patent_doc_number] => 20220199178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => Anti-fuse memory device, memory array, and programming method of an anti-fuse memory device for preventing leakage current and program disturbance [patent_app_type] => utility [patent_app_number] => 17/469828 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469828
Anti-fuse memory device, memory array, and programming method of an anti-fuse memory device for preventing leakage current and program disturbance Sep 7, 2021 Issued
Array ( [id] => 18304235 [patent_doc_number] => 11626147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Transmission circuit, transmission method, storage apparatus, and storage medium [patent_app_type] => utility [patent_app_number] => 17/467214 [patent_app_country] => US [patent_app_date] => 2021-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467214
Transmission circuit, transmission method, storage apparatus, and storage medium Sep 4, 2021 Issued
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