Huan Hoang

Array ( [id] => 4216942 [patent_doc_number] => 06078532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method and apparatus for improving performance of DRAM subsystems with SRAM overlays' [patent_app_type] => 1 [patent_app_number] => 9/241836 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4726 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078532.pdf [firstpage_image] =>[orig_patent_app_number] => 241836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4367325 [patent_doc_number] => 06292428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Semiconductor device reconciling different timing signals' [patent_app_type] => 1 [patent_app_number] => 9/240007 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 15771 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292428.pdf [firstpage_image] =>[orig_patent_app_number] => 240007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317294 [patent_doc_number] => 06188637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Semiconductor memory device allowing reduction in power consumption during standby' [patent_app_type] => 1 [patent_app_number] => 9/240001 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 52 [patent_no_of_words] => 22904 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188637.pdf [firstpage_image] =>[orig_patent_app_number] => 240001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4193884 [patent_doc_number] => 06021068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Nonvolatile semiconductor memory with read circuit using flip-flop type sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/238638 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6331 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021068.pdf [firstpage_image] =>[orig_patent_app_number] => 238638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170094 [patent_doc_number] => 06157560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Memory array datapath architecture' [patent_app_type] => 1 [patent_app_number] => 9/236509 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7376 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157560.pdf [firstpage_image] =>[orig_patent_app_number] => 236509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170034 [patent_doc_number] => 06108249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Semiconductor memory device having delay circuit for controlling timing of internal control signal' [patent_app_type] => 1 [patent_app_number] => 9/227938 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4899 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108249.pdf [firstpage_image] =>[orig_patent_app_number] => 227938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309727 [patent_doc_number] => 06185135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Robust wordline activation delay monitor using a plurality of sample wordlines' [patent_app_type] => 1 [patent_app_number] => 9/225340 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5218 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185135.pdf [firstpage_image] =>[orig_patent_app_number] => 225340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202132 [patent_doc_number] => 06154389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Semiconductor memory device with a column redundancy occupying a less chip area' [patent_app_type] => 1 [patent_app_number] => 9/222039 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6471 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154389.pdf [firstpage_image] =>[orig_patent_app_number] => 222039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120404 [patent_doc_number] => 06058042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Semiconductor nonvolatile memory device and method of data programming the same' [patent_app_type] => 1 [patent_app_number] => 9/219836 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 99 [patent_no_of_words] => 17304 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058042.pdf [firstpage_image] =>[orig_patent_app_number] => 219836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4284865 [patent_doc_number] => 06246615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Redundancy mapping in a multichip semiconductor package' [patent_app_type] => 1 [patent_app_number] => 9/219808 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246615.pdf [firstpage_image] =>[orig_patent_app_number] => 219808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120388 [patent_doc_number] => 06058041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'SEU hardening circuit' [patent_app_type] => 1 [patent_app_number] => 9/219807 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6878 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058041.pdf [firstpage_image] =>[orig_patent_app_number] => 219807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4331395 [patent_doc_number] => 06249472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Semiconductor memory device with antifuse' [patent_app_type] => 1 [patent_app_number] => 9/215109 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 84 [patent_no_of_words] => 7063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249472.pdf [firstpage_image] =>[orig_patent_app_number] => 215109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4065112 [patent_doc_number] => 05969998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'MOS semiconductor device with memory cells each having storage capacitor and transfer transistor' [patent_app_type] => 1 [patent_app_number] => 9/213773 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 47 [patent_no_of_words] => 12252 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969998.pdf [firstpage_image] =>[orig_patent_app_number] => 213773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4109089 [patent_doc_number] => 06049504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Pulse driver' [patent_app_type] => 1 [patent_app_number] => 9/211139 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2886 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049504.pdf [firstpage_image] =>[orig_patent_app_number] => 211139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131463 [patent_doc_number] => 06072742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Semiconductor memory device with a voltage down converter stably generating an internal down-converted voltage' [patent_app_type] => 1 [patent_app_number] => 9/210811 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 95 [patent_figures_cnt] => 147 [patent_no_of_words] => 80976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072742.pdf [firstpage_image] =>[orig_patent_app_number] => 210811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110824 [patent_doc_number] => 06067262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Redundancy analysis for embedded memories with built-in self test and built-in self repair' [patent_app_type] => 1 [patent_app_number] => 9/209938 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4723 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067262.pdf [firstpage_image] =>[orig_patent_app_number] => 209938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4148014 [patent_doc_number] => 06122211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Fast, low power, write scheme for memory circuits using pulsed off isolation device' [patent_app_type] => 1 [patent_app_number] => 9/208146 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6793 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122211.pdf [firstpage_image] =>[orig_patent_app_number] => 208146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261718 [patent_doc_number] => 06137725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method' [patent_app_type] => 1 [patent_app_number] => 9/203937 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4159 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137725.pdf [firstpage_image] =>[orig_patent_app_number] => 203937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250353 [patent_doc_number] => 06144581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'pMOS EEPROM non-volatile data storage' [patent_app_type] => 1 [patent_app_number] => 9/201327 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 6755 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144581.pdf [firstpage_image] =>[orig_patent_app_number] => 201327 [rel_patent_id] =>[rel_patent_doc_number] =>)