
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4417397
[patent_doc_number] => 06172908
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[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Controlled hot-electron writing method for non-volatile memory cells'
[patent_app_type] => 1
[patent_app_number] => 9/169239
[patent_app_country] => US
[patent_app_date] => 1998-10-08
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4048
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[pdf_file] => patents/06/172/06172908.pdf
[firstpage_image] =>[orig_patent_app_number] => 169239
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/169239 | Controlled hot-electron writing method for non-volatile memory cells | Oct 7, 1998 | Issued |
Array
(
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[patent_doc_number] => 06222790
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Semiconductor memory device in which data are read and written asynchronously with application of address signal'
[patent_app_type] => 1
[patent_app_number] => 9/166586
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[patent_app_date] => 1998-10-06
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[pdf_file] => patents/06/222/06222790.pdf
[firstpage_image] =>[orig_patent_app_number] => 166586
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/166586 | Semiconductor memory device in which data are read and written asynchronously with application of address signal | Oct 5, 1998 | Issued |
Array
(
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[patent_doc_number] => 06081448
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[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Method and device for analog programming of flash EEPROM memory cells with autoverify'
[patent_app_type] => 1
[patent_app_number] => 9/162639
[patent_app_country] => US
[patent_app_date] => 1998-09-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/162639 | Method and device for analog programming of flash EEPROM memory cells with autoverify | Sep 27, 1998 | Issued |
Array
(
[id] => 4367843
[patent_doc_number] => 06201734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-13
[patent_title] => 'Programmable impedance device'
[patent_app_type] => 1
[patent_app_number] => 9/159848
[patent_app_country] => US
[patent_app_date] => 1998-09-25
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 159848
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159848 | Programmable impedance device | Sep 24, 1998 | Issued |
Array
(
[id] => 4193898
[patent_doc_number] => 06021069
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Bit latch scheme for parallel program verify in floating gate memory device'
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[patent_app_number] => 9/160637
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[patent_app_date] => 1998-09-24
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[firstpage_image] =>[orig_patent_app_number] => 160637
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/160637 | Bit latch scheme for parallel program verify in floating gate memory device | Sep 23, 1998 | Issued |
Array
(
[id] => 4229838
[patent_doc_number] => 06111793
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Semiconductor device'
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[patent_app_number] => 9/158551
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/158551 | Semiconductor device | Sep 21, 1998 | Issued |
Array
(
[id] => 4093260
[patent_doc_number] => 06055175
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[patent_issue_date] => 2000-04-25
[patent_title] => 'Nonvolatile ferroelectric memory'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 157947
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157947 | Nonvolatile ferroelectric memory | Sep 21, 1998 | Issued |
Array
(
[id] => 4047831
[patent_doc_number] => 05995416
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[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Method and circuit for the generation of programming and erasure voltage in a non-volatile memory'
[patent_app_type] => 1
[patent_app_number] => 9/156945
[patent_app_country] => US
[patent_app_date] => 1998-09-18
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[pdf_file] => patents/05/995/05995416.pdf
[firstpage_image] =>[orig_patent_app_number] => 156945
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/156945 | Method and circuit for the generation of programming and erasure voltage in a non-volatile memory | Sep 17, 1998 | Issued |
Array
(
[id] => 3937598
[patent_doc_number] => 05946269
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Synchronous RAM controlling device and method'
[patent_app_type] => 1
[patent_app_number] => 9/156345
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/156345 | Synchronous RAM controlling device and method | Sep 17, 1998 | Issued |
Array
(
[id] => 4102608
[patent_doc_number] => 06134144
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[patent_issue_date] => 2000-10-17
[patent_title] => 'Flash memory array'
[patent_app_type] => 1
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[patent_app_date] => 1998-09-15
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[firstpage_image] =>[orig_patent_app_number] => 153843
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153843 | Flash memory array | Sep 14, 1998 | Issued |
Array
(
[id] => 3963553
[patent_doc_number] => 05978246
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[patent_issue_date] => 1999-11-02
[patent_title] => 'Content addressable memory device'
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[firstpage_image] =>[orig_patent_app_number] => 149439
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/149439 | Content addressable memory device | Sep 7, 1998 | Issued |
Array
(
[id] => 4115090
[patent_doc_number] => 06052321
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Circuit and method for performing test on memory array cells using external sense amplifier reference current'
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Array
(
[id] => 3937433
[patent_doc_number] => 05946259
[patent_country] => US
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[patent_issue_date] => 1999-08-31
[patent_title] => 'Voltage generator methods and apparatus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/144736 | Voltage generator methods and apparatus | Aug 31, 1998 | Issued |
Array
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Array
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Array
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[patent_title] => 'Memory device tracking circuit'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/131346 | Multi-bank semiconductor memory device suitable for integration with logic | Aug 6, 1998 | Issued |