
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4131065
[patent_doc_number] => 06072714
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Static memory cell with a pair of transfer MOS transistors, a pair of driver MOS transistors and a pair of load elements'
[patent_app_type] => 1
[patent_app_number] => 9/087648
[patent_app_country] => US
[patent_app_date] => 1998-05-29
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 9360
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[pdf_file] => patents/06/072/06072714.pdf
[firstpage_image] =>[orig_patent_app_number] => 087648
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/087648 | Static memory cell with a pair of transfer MOS transistors, a pair of driver MOS transistors and a pair of load elements | May 28, 1998 | Issued |
Array
(
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[patent_doc_number] => 05995421
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Circuit and method for reading a memory cell'
[patent_app_type] => 1
[patent_app_number] => 9/087399
[patent_app_country] => US
[patent_app_date] => 1998-05-29
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[pdf_file] => patents/05/995/05995421.pdf
[firstpage_image] =>[orig_patent_app_number] => 087399
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/087399 | Circuit and method for reading a memory cell | May 28, 1998 | Issued |
Array
(
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[patent_doc_number] => 05953273
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[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Semiconductor integrated circuit device having confirmable self-diagnostic function'
[patent_app_type] => 1
[patent_app_number] => 9/085059
[patent_app_country] => US
[patent_app_date] => 1998-05-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/085059 | Semiconductor integrated circuit device having confirmable self-diagnostic function | May 26, 1998 | Issued |
Array
(
[id] => 4010594
[patent_doc_number] => 05923592
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Fast, low power, write scheme for memory circuits using pulsed off isolation device'
[patent_app_type] => 1
[patent_app_number] => 9/080548
[patent_app_country] => US
[patent_app_date] => 1998-05-18
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 080548
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/080548 | Fast, low power, write scheme for memory circuits using pulsed off isolation device | May 17, 1998 | Issued |
Array
(
[id] => 4204930
[patent_doc_number] => 06044036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Buffer circuit, memory device, and integrated circuit for receiving digital signals'
[patent_app_type] => 1
[patent_app_number] => 9/078159
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[patent_app_date] => 1998-05-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/078159 | Buffer circuit, memory device, and integrated circuit for receiving digital signals | May 12, 1998 | Issued |
Array
(
[id] => 3961980
[patent_doc_number] => 05999438
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Ferroelectric storage device'
[patent_app_type] => 1
[patent_app_number] => 9/075346
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[patent_app_date] => 1998-05-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/075346 | Ferroelectric storage device | May 10, 1998 | Issued |
Array
(
[id] => 4047612
[patent_doc_number] => 05995401
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Large-capacity content addressable memory'
[patent_app_type] => 1
[patent_app_number] => 9/074653
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[patent_app_date] => 1998-05-08
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[pdf_file] => patents/05/995/05995401.pdf
[firstpage_image] =>[orig_patent_app_number] => 074653
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/074653 | Large-capacity content addressable memory | May 7, 1998 | Issued |
Array
(
[id] => 4115165
[patent_doc_number] => 06052326
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Chain-latch circuit achieving stable operations'
[patent_app_type] => 1
[patent_app_number] => 9/071162
[patent_app_country] => US
[patent_app_date] => 1998-05-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/052/06052326.pdf
[firstpage_image] =>[orig_patent_app_number] => 071162
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071162 | Chain-latch circuit achieving stable operations | May 3, 1998 | Issued |
Array
(
[id] => 4120619
[patent_doc_number] => 06058056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Data compression circuit and method for testing memory devices'
[patent_app_type] => 1
[patent_app_number] => 9/070558
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 070558
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070558 | Data compression circuit and method for testing memory devices | Apr 29, 1998 | Issued |
Array
(
[id] => 4185545
[patent_doc_number] => 06141270
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Method for cell margin testing a dynamic cell plate sensing memory architecture'
[patent_app_type] => 1
[patent_app_number] => 9/070520
[patent_app_country] => US
[patent_app_date] => 1998-04-29
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[pdf_file] => patents/06/141/06141270.pdf
[firstpage_image] =>[orig_patent_app_number] => 070520
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070520 | Method for cell margin testing a dynamic cell plate sensing memory architecture | Apr 28, 1998 | Issued |
Array
(
[id] => 4025595
[patent_doc_number] => 05963462
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method'
[patent_app_type] => 1
[patent_app_number] => 9/067642
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[patent_app_date] => 1998-04-27
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[firstpage_image] =>[orig_patent_app_number] => 067642
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/067642 | Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method | Apr 26, 1998 | Issued |
Array
(
[id] => 3957550
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Array
(
[id] => 3915476
[patent_doc_number] => 05898635
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[patent_title] => 'Power-up circuit responsive to supply voltage transients'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/063418 | Power-up circuit responsive to supply voltage transients | Apr 19, 1998 | Issued |
Array
(
[id] => 1546828
[patent_doc_number] => 06373747
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[patent_issue_date] => 2002-04-16
[patent_title] => 'Flash EEprom system'
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Array
(
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Array
(
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/049057 | Test method and circuit for semiconductor memory | Mar 26, 1998 | Issued |