Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4131065 [patent_doc_number] => 06072714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Static memory cell with a pair of transfer MOS transistors, a pair of driver MOS transistors and a pair of load elements' [patent_app_type] => 1 [patent_app_number] => 9/087648 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9360 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072714.pdf [firstpage_image] =>[orig_patent_app_number] => 087648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087648
Static memory cell with a pair of transfer MOS transistors, a pair of driver MOS transistors and a pair of load elements May 28, 1998 Issued
Array ( [id] => 4047899 [patent_doc_number] => 05995421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Circuit and method for reading a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/087399 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4032 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995421.pdf [firstpage_image] =>[orig_patent_app_number] => 087399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087399
Circuit and method for reading a memory cell May 28, 1998 Issued
Array ( [id] => 3940352 [patent_doc_number] => 05953273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Semiconductor integrated circuit device having confirmable self-diagnostic function' [patent_app_type] => 1 [patent_app_number] => 9/085059 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5524 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953273.pdf [firstpage_image] =>[orig_patent_app_number] => 085059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085059
Semiconductor integrated circuit device having confirmable self-diagnostic function May 26, 1998 Issued
Array ( [id] => 4010594 [patent_doc_number] => 05923592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Fast, low power, write scheme for memory circuits using pulsed off isolation device' [patent_app_type] => 1 [patent_app_number] => 9/080548 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6793 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923592.pdf [firstpage_image] =>[orig_patent_app_number] => 080548 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080548
Fast, low power, write scheme for memory circuits using pulsed off isolation device May 17, 1998 Issued
Array ( [id] => 4204930 [patent_doc_number] => 06044036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Buffer circuit, memory device, and integrated circuit for receiving digital signals' [patent_app_type] => 1 [patent_app_number] => 9/078159 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2803 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044036.pdf [firstpage_image] =>[orig_patent_app_number] => 078159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/078159
Buffer circuit, memory device, and integrated circuit for receiving digital signals May 12, 1998 Issued
Array ( [id] => 3961980 [patent_doc_number] => 05999438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Ferroelectric storage device' [patent_app_type] => 1 [patent_app_number] => 9/075346 [patent_app_country] => US [patent_app_date] => 1998-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4997 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999438.pdf [firstpage_image] =>[orig_patent_app_number] => 075346 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075346
Ferroelectric storage device May 10, 1998 Issued
Array ( [id] => 4047612 [patent_doc_number] => 05995401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Large-capacity content addressable memory' [patent_app_type] => 1 [patent_app_number] => 9/074653 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6029 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995401.pdf [firstpage_image] =>[orig_patent_app_number] => 074653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074653
Large-capacity content addressable memory May 7, 1998 Issued
Array ( [id] => 4115165 [patent_doc_number] => 06052326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Chain-latch circuit achieving stable operations' [patent_app_type] => 1 [patent_app_number] => 9/071162 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5494 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052326.pdf [firstpage_image] =>[orig_patent_app_number] => 071162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071162
Chain-latch circuit achieving stable operations May 3, 1998 Issued
Array ( [id] => 4120619 [patent_doc_number] => 06058056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Data compression circuit and method for testing memory devices' [patent_app_type] => 1 [patent_app_number] => 9/070558 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5402 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058056.pdf [firstpage_image] =>[orig_patent_app_number] => 070558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070558
Data compression circuit and method for testing memory devices Apr 29, 1998 Issued
Array ( [id] => 4185545 [patent_doc_number] => 06141270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method for cell margin testing a dynamic cell plate sensing memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/070520 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141270.pdf [firstpage_image] =>[orig_patent_app_number] => 070520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070520
Method for cell margin testing a dynamic cell plate sensing memory architecture Apr 28, 1998 Issued
Array ( [id] => 4025595 [patent_doc_number] => 05963462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method' [patent_app_type] => 1 [patent_app_number] => 9/067642 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7182 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963462.pdf [firstpage_image] =>[orig_patent_app_number] => 067642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067642
Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method Apr 26, 1998 Issued
Array ( [id] => 3957550 [patent_doc_number] => 05982695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/064047 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6712 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982695.pdf [firstpage_image] =>[orig_patent_app_number] => 064047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064047
Semiconductor memory Apr 21, 1998 Issued
Array ( [id] => 3915476 [patent_doc_number] => 05898635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Power-up circuit responsive to supply voltage transients' [patent_app_type] => 1 [patent_app_number] => 9/063418 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4059 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898635.pdf [firstpage_image] =>[orig_patent_app_number] => 063418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063418
Power-up circuit responsive to supply voltage transients Apr 19, 1998 Issued
Array ( [id] => 1546828 [patent_doc_number] => 06373747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Flash EEprom system' [patent_app_type] => B1 [patent_app_number] => 09/059815 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 37 [patent_no_of_words] => 18971 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373747.pdf [firstpage_image] =>[orig_patent_app_number] => 09059815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059815
Flash EEprom system Apr 13, 1998 Issued
Array ( [id] => 4065451 [patent_doc_number] => 05970021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Synchronous semiconductor memory device having function of inhibiting output of invalid data' [patent_app_type] => 1 [patent_app_number] => 9/058858 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8438 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970021.pdf [firstpage_image] =>[orig_patent_app_number] => 058858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058858
Synchronous semiconductor memory device having function of inhibiting output of invalid data Apr 12, 1998 Issued
Array ( [id] => 3998652 [patent_doc_number] => 05959926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Programmable power supply systems and methods providing a write protected memory having multiple interface capability' [patent_app_type] => 1 [patent_app_number] => 9/059244 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 11216 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959926.pdf [firstpage_image] =>[orig_patent_app_number] => 059244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059244
Programmable power supply systems and methods providing a write protected memory having multiple interface capability Apr 12, 1998 Issued
Array ( [id] => 4155403 [patent_doc_number] => 06031779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Dynamic memory' [patent_app_type] => 1 [patent_app_number] => 9/058147 [patent_app_country] => US [patent_app_date] => 1998-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 15355 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031779.pdf [firstpage_image] =>[orig_patent_app_number] => 058147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058147
Dynamic memory Apr 9, 1998 Issued
Array ( [id] => 3947404 [patent_doc_number] => 05940344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Synchronous semiconductor memory device including internal clock signal generation circuit that generates an internal clock signal synchronizing in phase with external clock signal at high precision' [patent_app_type] => 1 [patent_app_number] => 9/053058 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7130 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940344.pdf [firstpage_image] =>[orig_patent_app_number] => 053058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053058
Synchronous semiconductor memory device including internal clock signal generation circuit that generates an internal clock signal synchronizing in phase with external clock signal at high precision Mar 31, 1998 Issued
Array ( [id] => 7556475 [patent_doc_number] => 08068379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-29 [patent_title] => 'Dynamic RAM' [patent_app_type] => utility [patent_app_number] => 09/050946 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10696 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/068/08068379.pdf [firstpage_image] =>[orig_patent_app_number] => 09050946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050946
Dynamic RAM Mar 30, 1998 Issued
Array ( [id] => 4078157 [patent_doc_number] => 06009027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Test method and circuit for semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/049057 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3954 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009027.pdf [firstpage_image] =>[orig_patent_app_number] => 049057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049057
Test method and circuit for semiconductor memory Mar 26, 1998 Issued
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