Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4054708 [patent_doc_number] => 05912859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method for the resetting of a shift register and associated register' [patent_app_type] => 1 [patent_app_number] => 9/049644 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2014 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912859.pdf [firstpage_image] =>[orig_patent_app_number] => 049644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049644
Method for the resetting of a shift register and associated register Mar 26, 1998 Issued
Array ( [id] => 4047734 [patent_doc_number] => 05995409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Electrically-programmable read-only memory fabricated using a dynamic random access memory fabrication process and methods for programming same' [patent_app_type] => 1 [patent_app_number] => 9/045259 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 8667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995409.pdf [firstpage_image] =>[orig_patent_app_number] => 045259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045259
Electrically-programmable read-only memory fabricated using a dynamic random access memory fabrication process and methods for programming same Mar 19, 1998 Issued
Array ( [id] => 3964246 [patent_doc_number] => 05978293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Circuitry and methods for dynamically sensing of data in a static random access memory cell' [patent_app_type] => 1 [patent_app_number] => 9/045757 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4074 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978293.pdf [firstpage_image] =>[orig_patent_app_number] => 045757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045757
Circuitry and methods for dynamically sensing of data in a static random access memory cell Mar 18, 1998 Issued
Array ( [id] => 4247314 [patent_doc_number] => 06118705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Page mode erase in a flash memory array' [patent_app_type] => 1 [patent_app_number] => 9/042244 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4669 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118705.pdf [firstpage_image] =>[orig_patent_app_number] => 042244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042244
Page mode erase in a flash memory array Mar 12, 1998 Issued
Array ( [id] => 4197080 [patent_doc_number] => 06094373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/031240 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 12316 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094373.pdf [firstpage_image] =>[orig_patent_app_number] => 031240 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031240
Nonvolatile semiconductor memory device Feb 25, 1998 Issued
Array ( [id] => 4265834 [patent_doc_number] => 06208548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Slave circuit select device which can individually select a plurality of slave circuits with one data bus' [patent_app_type] => 1 [patent_app_number] => 9/025838 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5056 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208548.pdf [firstpage_image] =>[orig_patent_app_number] => 025838 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025838
Slave circuit select device which can individually select a plurality of slave circuits with one data bus Feb 18, 1998 Issued
Array ( [id] => 4048035 [patent_doc_number] => 05995430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/025860 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 12628 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995430.pdf [firstpage_image] =>[orig_patent_app_number] => 025860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025860
Semiconductor memory device Feb 18, 1998 Issued
Array ( [id] => 4144605 [patent_doc_number] => 06016267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'High speed, high bandwidth, high density, nonvolatile memory system' [patent_app_type] => 1 [patent_app_number] => 9/024759 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016267.pdf [firstpage_image] =>[orig_patent_app_number] => 024759 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024759
High speed, high bandwidth, high density, nonvolatile memory system Feb 16, 1998 Issued
Array ( [id] => 3998817 [patent_doc_number] => 05959937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Dual clocking scheme in a multi-port RAM' [patent_app_type] => 1 [patent_app_number] => 9/024559 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3957 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959937.pdf [firstpage_image] =>[orig_patent_app_number] => 024559 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024559
Dual clocking scheme in a multi-port RAM Feb 16, 1998 Issued
Array ( [id] => 4025706 [patent_doc_number] => 05963470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Static semiconductor memory cell with improved data retention stability' [patent_app_type] => 1 [patent_app_number] => 9/019560 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3204 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963470.pdf [firstpage_image] =>[orig_patent_app_number] => 019560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019560
Static semiconductor memory cell with improved data retention stability Feb 5, 1998 Issued
Array ( [id] => 4026163 [patent_doc_number] => 05963499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Cascadable multi-channel network memory with dynamic allocation' [patent_app_type] => 1 [patent_app_number] => 9/018758 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3733 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963499.pdf [firstpage_image] =>[orig_patent_app_number] => 018758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018758
Cascadable multi-channel network memory with dynamic allocation Feb 4, 1998 Issued
Array ( [id] => 4025676 [patent_doc_number] => 05963468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Low latency memories and systems using the same' [patent_app_type] => 1 [patent_app_number] => 9/016559 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6089 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963468.pdf [firstpage_image] =>[orig_patent_app_number] => 016559 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/016559
Low latency memories and systems using the same Jan 29, 1998 Issued
Array ( [id] => 4144123 [patent_doc_number] => 06034883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Solid state director for beams' [patent_app_type] => 1 [patent_app_number] => 9/015536 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6414 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034883.pdf [firstpage_image] =>[orig_patent_app_number] => 015536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015536
Solid state director for beams Jan 28, 1998 Issued
Array ( [id] => 4147919 [patent_doc_number] => 06122205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Voltage regulator and boosting circuit for reading a memory cell at low voltage levels' [patent_app_type] => 1 [patent_app_number] => 9/014458 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3078 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122205.pdf [firstpage_image] =>[orig_patent_app_number] => 014458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014458
Voltage regulator and boosting circuit for reading a memory cell at low voltage levels Jan 27, 1998 Issued
Array ( [id] => 3937261 [patent_doc_number] => 05946247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Semiconductor memory testing device' [patent_app_type] => 1 [patent_app_number] => 9/013062 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 141 [patent_figures_cnt] => 158 [patent_no_of_words] => 56552 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946247.pdf [firstpage_image] =>[orig_patent_app_number] => 013062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013062
Semiconductor memory testing device Jan 25, 1998 Issued
Array ( [id] => 4017708 [patent_doc_number] => 06005818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Dynamic random access memory device with a latching mechanism that permits hidden refresh operations' [patent_app_type] => 1 [patent_app_number] => 9/009343 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005818.pdf [firstpage_image] =>[orig_patent_app_number] => 009343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009343
Dynamic random access memory device with a latching mechanism that permits hidden refresh operations Jan 19, 1998 Issued
Array ( [id] => 4086105 [patent_doc_number] => 05966319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Static memory device allowing correct data reading' [patent_app_type] => 1 [patent_app_number] => 9/009162 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 16700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966319.pdf [firstpage_image] =>[orig_patent_app_number] => 009162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009162
Static memory device allowing correct data reading Jan 19, 1998 Issued
Array ( [id] => 3988868 [patent_doc_number] => 05917773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Apparatus and method for writing to multiple addresses' [patent_app_type] => 1 [patent_app_number] => 9/007257 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3655 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917773.pdf [firstpage_image] =>[orig_patent_app_number] => 007257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007257
Apparatus and method for writing to multiple addresses Jan 13, 1998 Issued
Array ( [id] => 4198006 [patent_doc_number] => 06151269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof' [patent_app_type] => 1 [patent_app_number] => 9/007229 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 191 [patent_figures_cnt] => 248 [patent_no_of_words] => 90511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151269.pdf [firstpage_image] =>[orig_patent_app_number] => 007229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007229
Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof Jan 13, 1998 Issued
Array ( [id] => 4017694 [patent_doc_number] => 06005817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method for parallel writing and reading of data in an optical memory, a writing/reading device for use by the method and uses of the method and the writing/reading device' [patent_app_type] => 1 [patent_app_number] => 8/981661 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5945 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005817.pdf [firstpage_image] =>[orig_patent_app_number] => 981661 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/981661
Method for parallel writing and reading of data in an optical memory, a writing/reading device for use by the method and uses of the method and the writing/reading device Jan 7, 1998 Issued
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