
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4054708
[patent_doc_number] => 05912859
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Method for the resetting of a shift register and associated register'
[patent_app_type] => 1
[patent_app_number] => 9/049644
[patent_app_country] => US
[patent_app_date] => 1998-03-27
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[pdf_file] => patents/05/912/05912859.pdf
[firstpage_image] =>[orig_patent_app_number] => 049644
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/049644 | Method for the resetting of a shift register and associated register | Mar 26, 1998 | Issued |
Array
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[patent_issue_date] => 1999-11-30
[patent_title] => 'Electrically-programmable read-only memory fabricated using a dynamic random access memory fabrication process and methods for programming same'
[patent_app_type] => 1
[patent_app_number] => 9/045259
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[patent_app_date] => 1998-03-20
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Array
(
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[patent_doc_number] => 05978293
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[patent_issue_date] => 1999-11-02
[patent_title] => 'Circuitry and methods for dynamically sensing of data in a static random access memory cell'
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[patent_app_number] => 9/045757
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Array
(
[id] => 4247314
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[patent_country] => US
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[patent_issue_date] => 2000-09-12
[patent_title] => 'Page mode erase in a flash memory array'
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[patent_app_number] => 9/042244
[patent_app_country] => US
[patent_app_date] => 1998-03-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/042244 | Page mode erase in a flash memory array | Mar 12, 1998 | Issued |
Array
(
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[patent_doc_number] => 06094373
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[patent_issue_date] => 2000-07-25
[patent_title] => 'Nonvolatile semiconductor memory device'
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Array
(
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[patent_title] => 'Slave circuit select device which can individually select a plurality of slave circuits with one data bus'
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Array
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Array
(
[id] => 4144605
[patent_doc_number] => 06016267
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[patent_issue_date] => 2000-01-18
[patent_title] => 'High speed, high bandwidth, high density, nonvolatile memory system'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/024759 | High speed, high bandwidth, high density, nonvolatile memory system | Feb 16, 1998 | Issued |
Array
(
[id] => 3998817
[patent_doc_number] => 05959937
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[patent_issue_date] => 1999-09-28
[patent_title] => 'Dual clocking scheme in a multi-port RAM'
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Array
(
[id] => 4025706
[patent_doc_number] => 05963470
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[patent_issue_date] => 1999-10-05
[patent_title] => 'Static semiconductor memory cell with improved data retention stability'
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Array
(
[id] => 4026163
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[patent_title] => 'Cascadable multi-channel network memory with dynamic allocation'
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Array
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[patent_title] => 'Low latency memories and systems using the same'
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Array
(
[id] => 4144123
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[patent_title] => 'Solid state director for beams'
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Array
(
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[patent_issue_date] => 2000-09-19
[patent_title] => 'Voltage regulator and boosting circuit for reading a memory cell at low voltage levels'
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Array
(
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Array
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Array
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