Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3998080 [patent_doc_number] => 05959889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Counter-bias scheme to reduce charge gain in an electrically erasable cell' [patent_app_type] => 1 [patent_app_number] => 8/998258 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4045 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959889.pdf [firstpage_image] =>[orig_patent_app_number] => 998258 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998258
Counter-bias scheme to reduce charge gain in an electrically erasable cell Dec 28, 1997 Issued
Array ( [id] => 3940447 [patent_doc_number] => 05953279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Fuse option circuit for memory device' [patent_app_type] => 1 [patent_app_number] => 8/999257 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2920 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953279.pdf [firstpage_image] =>[orig_patent_app_number] => 999257 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999257
Fuse option circuit for memory device Dec 28, 1997 Issued
Array ( [id] => 4073358 [patent_doc_number] => 05896332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method and apparatus for measuring the offset voltages of SRAM sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 8/998420 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4295 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896332.pdf [firstpage_image] =>[orig_patent_app_number] => 998420 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998420
Method and apparatus for measuring the offset voltages of SRAM sense amplifiers Dec 23, 1997 Issued
Array ( [id] => 4064462 [patent_doc_number] => 05933384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/997558 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11502 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933384.pdf [firstpage_image] =>[orig_patent_app_number] => 997558 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997558
Semiconductor integrated circuit Dec 22, 1997 Issued
Array ( [id] => 4054433 [patent_doc_number] => 05912841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Repair fuse circuit performing complete latch operation using flash memory cell' [patent_app_type] => 1 [patent_app_number] => 8/997063 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2077 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912841.pdf [firstpage_image] =>[orig_patent_app_number] => 997063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997063
Repair fuse circuit performing complete latch operation using flash memory cell Dec 22, 1997 Issued
Array ( [id] => 4078200 [patent_doc_number] => 06009030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Sense amplifier enable signal generating circuit of semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 8/995637 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3943 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009030.pdf [firstpage_image] =>[orig_patent_app_number] => 995637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995637
Sense amplifier enable signal generating circuit of semiconductor memory devices Dec 21, 1997 Issued
Array ( [id] => 4214123 [patent_doc_number] => 06028455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof' [patent_app_type] => 1 [patent_app_number] => 8/994128 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 14353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028455.pdf [firstpage_image] =>[orig_patent_app_number] => 994128 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994128
Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof Dec 18, 1997 Issued
Array ( [id] => 3947356 [patent_doc_number] => 05940341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/991363 [patent_app_country] => US [patent_app_date] => 1997-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4366 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940341.pdf [firstpage_image] =>[orig_patent_app_number] => 991363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991363
Semiconductor memory device Dec 14, 1997 Issued
Array ( [id] => 3962186 [patent_doc_number] => 05956271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Channel hot electron programmed memory device having improved reliability and operability' [patent_app_type] => 1 [patent_app_number] => 8/989959 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1830 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956271.pdf [firstpage_image] =>[orig_patent_app_number] => 989959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989959
Channel hot electron programmed memory device having improved reliability and operability Dec 11, 1997 Issued
Array ( [id] => 3969903 [patent_doc_number] => 05936878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Polymeric photo-chromic composition' [patent_app_type] => 1 [patent_app_number] => 8/989460 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4511 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936878.pdf [firstpage_image] =>[orig_patent_app_number] => 989460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989460
Polymeric photo-chromic composition Dec 11, 1997 Issued
Array ( [id] => 4025762 [patent_doc_number] => 05963473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks' [patent_app_type] => 1 [patent_app_number] => 8/989523 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10815 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963473.pdf [firstpage_image] =>[orig_patent_app_number] => 989523 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989523
Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks Dec 11, 1997 Issued
Array ( [id] => 4209319 [patent_doc_number] => 06014329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Flash-erasable semiconductor memory device having an improved reliability' [patent_app_type] => 1 [patent_app_number] => 8/986337 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 47 [patent_no_of_words] => 16951 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014329.pdf [firstpage_image] =>[orig_patent_app_number] => 986337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986337
Flash-erasable semiconductor memory device having an improved reliability Dec 4, 1997 Issued
Array ( [id] => 3824588 [patent_doc_number] => 05812440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 8/985465 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 18698 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812440.pdf [firstpage_image] =>[orig_patent_app_number] => 985465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985465
Semiconductor storage device Dec 3, 1997 Issued
Array ( [id] => 4025662 [patent_doc_number] => 05963467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/982457 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 12210 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963467.pdf [firstpage_image] =>[orig_patent_app_number] => 982457 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982457
Semiconductor memory device Dec 1, 1997 Issued
Array ( [id] => 4005261 [patent_doc_number] => 05892730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Synchronous semiconductor memory device operable in a plurality of data write operation modes' [patent_app_type] => 1 [patent_app_number] => 8/980963 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 23711 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892730.pdf [firstpage_image] =>[orig_patent_app_number] => 980963 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980963
Synchronous semiconductor memory device operable in a plurality of data write operation modes Nov 30, 1997 Issued
Array ( [id] => 3889303 [patent_doc_number] => 05825685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'High-speed, low-current magnetoresistive memory device' [patent_app_type] => 1 [patent_app_number] => 8/979791 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 6913 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825685.pdf [firstpage_image] =>[orig_patent_app_number] => 979791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979791
High-speed, low-current magnetoresistive memory device Nov 25, 1997 Issued
Array ( [id] => 4038588 [patent_doc_number] => 05903502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Variable equilibrate voltage circuit for paired digit lines' [patent_app_type] => 1 [patent_app_number] => 8/977757 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3710 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903502.pdf [firstpage_image] =>[orig_patent_app_number] => 977757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977757
Variable equilibrate voltage circuit for paired digit lines Nov 24, 1997 Issued
Array ( [id] => 4038357 [patent_doc_number] => 05903487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Memory device and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/978157 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 5818 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903487.pdf [firstpage_image] =>[orig_patent_app_number] => 978157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978157
Memory device and method of operation Nov 24, 1997 Issued
Array ( [id] => 4012025 [patent_doc_number] => 05986934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Semiconductor memory array with buried drain lines and methods therefor' [patent_app_type] => 1 [patent_app_number] => 8/977647 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7710 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986934.pdf [firstpage_image] =>[orig_patent_app_number] => 977647 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977647
Semiconductor memory array with buried drain lines and methods therefor Nov 23, 1997 Issued
Array ( [id] => 4065408 [patent_doc_number] => 05970018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Semiconductor integrated circuit and decode circuit for memory' [patent_app_type] => 1 [patent_app_number] => 8/974560 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 10221 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970018.pdf [firstpage_image] =>[orig_patent_app_number] => 974560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974560
Semiconductor integrated circuit and decode circuit for memory Nov 18, 1997 Issued
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