Huan Hoang

Array ( [id] => 4027334 [patent_doc_number] => 05907517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Memory circuit yield generator and timing adjustor' [patent_app_type] => 1 [patent_app_number] => 8/967878 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 39 [patent_no_of_words] => 28952 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907517.pdf [firstpage_image] =>[orig_patent_app_number] => 967878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4027293 [patent_doc_number] => 05881007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Sense amplifier enable signal generator for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/965861 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 1706 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881007.pdf [firstpage_image] =>[orig_patent_app_number] => 965861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970860 [patent_doc_number] => 05901080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/967264 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1850 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901080.pdf [firstpage_image] =>[orig_patent_app_number] => 967264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4034545 [patent_doc_number] => 05926423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Wafer burn-in circuit for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/964647 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2309 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926423.pdf [firstpage_image] =>[orig_patent_app_number] => 964647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932671 [patent_doc_number] => 05914905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/964360 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4761 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914905.pdf [firstpage_image] =>[orig_patent_app_number] => 964360 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145331 [patent_doc_number] => 06147908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Stable adjustable programming voltage scheme' [patent_app_type] => 1 [patent_app_number] => 8/962860 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147908.pdf [firstpage_image] =>[orig_patent_app_number] => 962860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3957461 [patent_doc_number] => 05982689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Amplifier circuit of latch type which is used for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/962659 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7833 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982689.pdf [firstpage_image] =>[orig_patent_app_number] => 962659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950699 [patent_doc_number] => 05930187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'One-chip LSI including a general memory and a logic' [patent_app_type] => 1 [patent_app_number] => 8/962358 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5658 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930187.pdf [firstpage_image] =>[orig_patent_app_number] => 962358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4027146 [patent_doc_number] => 05880998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced' [patent_app_type] => 1 [patent_app_number] => 8/960268 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 13566 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880998.pdf [firstpage_image] =>[orig_patent_app_number] => 960268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3962393 [patent_doc_number] => 05956286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Data processing system and method for implementing a multi-port memory cell' [patent_app_type] => 1 [patent_app_number] => 8/958559 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9019 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956286.pdf [firstpage_image] =>[orig_patent_app_number] => 958559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3994239 [patent_doc_number] => 05949735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Row decoder for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/956361 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4712 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949735.pdf [firstpage_image] =>[orig_patent_app_number] => 956361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892210 [patent_doc_number] => 05805510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Data erase mechanism for nonvolatile memory of boot block type' [patent_app_type] => 1 [patent_app_number] => 8/953388 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 12252 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805510.pdf [firstpage_image] =>[orig_patent_app_number] => 953388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4103022 [patent_doc_number] => 06134174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Semiconductor memory for logic-hybrid memory' [patent_app_type] => 1 [patent_app_number] => 8/949762 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3976 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134174.pdf [firstpage_image] =>[orig_patent_app_number] => 949762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915303 [patent_doc_number] => 05898623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Input port switching protocol for a random access memory' [patent_app_type] => 1 [patent_app_number] => 8/947762 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2231 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898623.pdf [firstpage_image] =>[orig_patent_app_number] => 947762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971358 [patent_doc_number] => 05901109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Semiconductor memory device capable of higher-speed operation and activated in synchronism with clock' [patent_app_type] => 1 [patent_app_number] => 8/941656 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6893 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901109.pdf [firstpage_image] =>[orig_patent_app_number] => 941656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4010792 [patent_doc_number] => 05923605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Space-efficient semiconductor memory having hierarchical column select line architecture' [patent_app_type] => 1 [patent_app_number] => 8/940861 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923605.pdf [firstpage_image] =>[orig_patent_app_number] => 940861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4005315 [patent_doc_number] => 05920515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/938062 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6657 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920515.pdf [firstpage_image] =>[orig_patent_app_number] => 938062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015209 [patent_doc_number] => 05859804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method and apparatus for real time two dimensional redundancy allocation' [patent_app_type] => 1 [patent_app_number] => 8/938757 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10151 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859804.pdf [firstpage_image] =>[orig_patent_app_number] => 938757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4005342 [patent_doc_number] => 05920517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Memory array test and characterization using isolated memory cell power supply' [patent_app_type] => 1 [patent_app_number] => 8/938257 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 17219 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920517.pdf [firstpage_image] =>[orig_patent_app_number] => 938257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4037030 [patent_doc_number] => 05883834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Low power consuming memory sense amplifying circuitry' [patent_app_type] => 1 [patent_app_number] => 8/937561 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7213 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883834.pdf [firstpage_image] =>[orig_patent_app_number] => 937561 [rel_patent_id] =>[rel_patent_doc_number] =>)