
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4010843
[patent_doc_number] => 05923609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Strobed wordline driver for fast memories'
[patent_app_type] => 1
[patent_app_number] => 8/933159
[patent_app_country] => US
[patent_app_date] => 1997-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2816
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/923/05923609.pdf
[firstpage_image] =>[orig_patent_app_number] => 933159
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/933159 | Strobed wordline driver for fast memories | Sep 17, 1997 | Issued |
Array
(
[id] => 4045563
[patent_doc_number] => 05856941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'One-time programmable latch which allows volatile writes prior to permanent programming'
[patent_app_type] => 1
[patent_app_number] => 8/929457
[patent_app_country] => US
[patent_app_date] => 1997-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5334
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 367
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/856/05856941.pdf
[firstpage_image] =>[orig_patent_app_number] => 929457
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/929457 | One-time programmable latch which allows volatile writes prior to permanent programming | Sep 14, 1997 | Issued |
Array
(
[id] => 4086220
[patent_doc_number] => 05966326
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Nonvolatile semiconductor memory equipped with single bit and multi-bit cells'
[patent_app_type] => 1
[patent_app_number] => 8/928121
[patent_app_country] => US
[patent_app_date] => 1997-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2928
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/966/05966326.pdf
[firstpage_image] =>[orig_patent_app_number] => 928121
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/928121 | Nonvolatile semiconductor memory equipped with single bit and multi-bit cells | Sep 11, 1997 | Issued |
Array
(
[id] => 3802824
[patent_doc_number] => 05841729
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Semiconductor memory device in which data are read and written asynchronously with application of address signal'
[patent_app_type] => 1
[patent_app_number] => 8/950049
[patent_app_country] => US
[patent_app_date] => 1997-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 24
[patent_no_of_words] => 7756
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841729.pdf
[firstpage_image] =>[orig_patent_app_number] => 950049
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/950049 | Semiconductor memory device in which data are read and written asynchronously with application of address signal | Sep 10, 1997 | Issued |
Array
(
[id] => 3994193
[patent_doc_number] => 05949732
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Method of structuring a multi-bank DRAM into a hierarchical column select line architecture'
[patent_app_type] => 1
[patent_app_number] => 8/927160
[patent_app_country] => US
[patent_app_date] => 1997-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4233
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/949/05949732.pdf
[firstpage_image] =>[orig_patent_app_number] => 927160
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/927160 | Method of structuring a multi-bank DRAM into a hierarchical column select line architecture | Sep 10, 1997 | Issued |
Array
(
[id] => 3798269
[patent_doc_number] => 05822268
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Hierarchical column select line architecture for multi-bank DRAMs'
[patent_app_type] => 1
[patent_app_number] => 8/927158
[patent_app_country] => US
[patent_app_date] => 1997-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4291
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822268.pdf
[firstpage_image] =>[orig_patent_app_number] => 927158
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/927158 | Hierarchical column select line architecture for multi-bank DRAMs | Sep 10, 1997 | Issued |
Array
(
[id] => 3824909
[patent_doc_number] => 05812457
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Semiconductor NAND type flash memory with incremental step pulse programming'
[patent_app_type] => 1
[patent_app_number] => 8/925662
[patent_app_country] => US
[patent_app_date] => 1997-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9961
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/812/05812457.pdf
[firstpage_image] =>[orig_patent_app_number] => 925662
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/925662 | Semiconductor NAND type flash memory with incremental step pulse programming | Sep 8, 1997 | Issued |
Array
(
[id] => 3900889
[patent_doc_number] => 05777937
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Regressive drive sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/927360
[patent_app_country] => US
[patent_app_date] => 1997-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5870
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/777/05777937.pdf
[firstpage_image] =>[orig_patent_app_number] => 927360
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/927360 | Regressive drive sense amplifier | Sep 8, 1997 | Issued |
Array
(
[id] => 3791907
[patent_doc_number] => 05818751
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Single-port SRAM with no read/write collisions'
[patent_app_type] => 1
[patent_app_number] => 8/925358
[patent_app_country] => US
[patent_app_date] => 1997-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3925
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/818/05818751.pdf
[firstpage_image] =>[orig_patent_app_number] => 925358
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/925358 | Single-port SRAM with no read/write collisions | Sep 7, 1997 | Issued |
Array
(
[id] => 4073565
[patent_doc_number] => 05896347
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same'
[patent_app_type] => 1
[patent_app_number] => 8/925458
[patent_app_country] => US
[patent_app_date] => 1997-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 5779
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/896/05896347.pdf
[firstpage_image] =>[orig_patent_app_number] => 925458
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/925458 | Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same | Sep 7, 1997 | Issued |
Array
(
[id] => 3986539
[patent_doc_number] => 05905682
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Method and apparatus for biasing the substrate of an integrated circuit to an externally adjustable voltage'
[patent_app_type] => 1
[patent_app_number] => 8/921863
[patent_app_country] => US
[patent_app_date] => 1997-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3920
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/905/05905682.pdf
[firstpage_image] =>[orig_patent_app_number] => 921863
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/921863 | Method and apparatus for biasing the substrate of an integrated circuit to an externally adjustable voltage | Aug 21, 1997 | Issued |
Array
(
[id] => 3885344
[patent_doc_number] => RE036203
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Semiconductor memory circuit'
[patent_app_type] => 2
[patent_app_number] => 8/916280
[patent_app_country] => US
[patent_app_date] => 1997-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3991
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 19
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/036/RE036203.pdf
[firstpage_image] =>[orig_patent_app_number] => 916280
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/916280 | Semiconductor memory circuit | Aug 21, 1997 | Issued |
Array
(
[id] => 3873651
[patent_doc_number] => 05793673
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Double polysilicon EEPROM cell and corresponding manufacturing process and programming method'
[patent_app_type] => 1
[patent_app_number] => 8/914518
[patent_app_country] => US
[patent_app_date] => 1997-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 23
[patent_no_of_words] => 3105
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/793/05793673.pdf
[firstpage_image] =>[orig_patent_app_number] => 914518
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/914518 | Double polysilicon EEPROM cell and corresponding manufacturing process and programming method | Aug 18, 1997 | Issued |
Array
(
[id] => 4027389
[patent_doc_number] => 05881014
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Semiconductor memory device with a voltage down converter stably generating an internal down-converter voltage'
[patent_app_type] => 1
[patent_app_number] => 8/914280
[patent_app_country] => US
[patent_app_date] => 1997-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 95
[patent_figures_cnt] => 147
[patent_no_of_words] => 80986
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/881/05881014.pdf
[firstpage_image] =>[orig_patent_app_number] => 914280
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/914280 | Semiconductor memory device with a voltage down converter stably generating an internal down-converter voltage | Aug 18, 1997 | Issued |
Array
(
[id] => 3837643
[patent_doc_number] => 05784318
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Method of preprogramming before verifying in non-volatile memory device and apparatus for the same'
[patent_app_type] => 1
[patent_app_number] => 8/908058
[patent_app_country] => US
[patent_app_date] => 1997-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 24
[patent_no_of_words] => 5857
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784318.pdf
[firstpage_image] =>[orig_patent_app_number] => 908058
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/908058 | Method of preprogramming before verifying in non-volatile memory device and apparatus for the same | Aug 10, 1997 | Issued |
Array
(
[id] => 3830599
[patent_doc_number] => 05790461
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Register file with bypass capability'
[patent_app_type] => 1
[patent_app_number] => 8/905034
[patent_app_country] => US
[patent_app_date] => 1997-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2067
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/790/05790461.pdf
[firstpage_image] =>[orig_patent_app_number] => 905034
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/905034 | Register file with bypass capability | Jul 31, 1997 | Issued |
Array
(
[id] => 4120525
[patent_doc_number] => 06058051
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Memory cell of non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/901660
[patent_app_country] => US
[patent_app_date] => 1997-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 47
[patent_no_of_words] => 13550
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/058/06058051.pdf
[firstpage_image] =>[orig_patent_app_number] => 901660
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/901660 | Memory cell of non-volatile semiconductor memory device | Jul 27, 1997 | Issued |
Array
(
[id] => 3905250
[patent_doc_number] => 05835430
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Method of providing redundancy in electrically alterable memories'
[patent_app_type] => 1
[patent_app_number] => 8/900262
[patent_app_country] => US
[patent_app_date] => 1997-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 4767
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/835/05835430.pdf
[firstpage_image] =>[orig_patent_app_number] => 900262
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/900262 | Method of providing redundancy in electrically alterable memories | Jul 24, 1997 | Issued |
Array
(
[id] => 4384657
[patent_doc_number] => 06288969
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Multi-port random access memory'
[patent_app_type] => 1
[patent_app_number] => 8/899818
[patent_app_country] => US
[patent_app_date] => 1997-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 12822
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/288/06288969.pdf
[firstpage_image] =>[orig_patent_app_number] => 899818
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/899818 | Multi-port random access memory | Jul 23, 1997 | Issued |
Array
(
[id] => 3792073
[patent_doc_number] => 05818761
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Non-volatile semiconductor memory device capable of high speed programming/erasure'
[patent_app_type] => 1
[patent_app_number] => 8/897101
[patent_app_country] => US
[patent_app_date] => 1997-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 63
[patent_no_of_words] => 28019
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/818/05818761.pdf
[firstpage_image] =>[orig_patent_app_number] => 897101
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/897101 | Non-volatile semiconductor memory device capable of high speed programming/erasure | Jul 17, 1997 | Issued |