Search

Huan Hoang

Examiner (ID: 15690, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818, 2154
Total Applications
3289
Issued Applications
3066
Pending Applications
115
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18500269 [patent_doc_number] => 20230223054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => LATCH ARRAY WITH MASK-WRITE FUNCTIONALITY [patent_app_type] => utility [patent_app_number] => 17/574431 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574431
Latch array with mask-write functionality Jan 11, 2022 Issued
Array ( [id] => 17630297 [patent_doc_number] => 20220165312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => USING EMBEDDED SWITCHES FOR REDUCING CAPACITIVE LOADING ON A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/572370 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572370
Using embedded switches for reducing capacitive loading on a memory system Jan 9, 2022 Issued
Array ( [id] => 19328622 [patent_doc_number] => 12046311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Semiconductor device, OTP readout circuit, and OTP circuit [patent_app_type] => utility [patent_app_number] => 17/568472 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5100 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568472
Semiconductor device, OTP readout circuit, and OTP circuit Jan 3, 2022 Issued
Array ( [id] => 18360699 [patent_doc_number] => 20230142290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => VERTICAL MEMORY DEVICES AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/646549 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646549
Vertical memory devices and methods for operating the same Dec 29, 2021 Issued
Array ( [id] => 17551310 [patent_doc_number] => 20220122652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => REFRESH MANAGEMENT FOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/564575 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564575 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564575
Refresh management for memory Dec 28, 2021 Issued
Array ( [id] => 17949012 [patent_doc_number] => 20220336031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => Bit Selection for Power Reduction in Stacking Structure During Memory Programming [patent_app_type] => utility [patent_app_number] => 17/557268 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557268
Bit selection for power reduction in stacking structure during memory programming Dec 20, 2021 Issued
Array ( [id] => 18874461 [patent_doc_number] => 11862282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => One transistor memory bitcell with arithmetic capability [patent_app_type] => utility [patent_app_number] => 17/555474 [patent_app_country] => US [patent_app_date] => 2021-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555474 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555474
One transistor memory bitcell with arithmetic capability Dec 18, 2021 Issued
Array ( [id] => 18607844 [patent_doc_number] => 11749320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Storage device and control method thereof [patent_app_type] => utility [patent_app_number] => 17/554512 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554512 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554512
Storage device and control method thereof Dec 16, 2021 Issued
Array ( [id] => 18950764 [patent_doc_number] => 11894067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate [patent_app_type] => utility [patent_app_number] => 17/551640 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 13968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551640 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551640
Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate Dec 14, 2021 Issued
Array ( [id] => 17508788 [patent_doc_number] => 20220101891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => BIASING ELECTRONIC COMPONENTS USING ADJUSTABLE CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/546026 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546026
Biasing electronic components using adjustable circuitry Dec 7, 2021 Issued
Array ( [id] => 18688136 [patent_doc_number] => 11783879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Memory device comprising programmable command-and-address and/or data interfaces [patent_app_type] => utility [patent_app_number] => 17/531151 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 6413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531151
Memory device comprising programmable command-and-address and/or data interfaces Nov 18, 2021 Issued
Array ( [id] => 17463433 [patent_doc_number] => 20220076739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY CONTEXT RESTORE, REDUCTION OF BOOT TIME OF A SYSTEM ON A CHIP BY REDUCING DOUBLE DATA RATE MEMORY TRAINING [patent_app_type] => utility [patent_app_number] => 17/526429 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526429
Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training Nov 14, 2021 Issued
Array ( [id] => 18170462 [patent_doc_number] => 20230037073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => MEMORY DEVICE RELATED TO PERFORMING A COLUMN OPERATION [patent_app_type] => utility [patent_app_number] => 17/524307 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524307
Memory device related to performing a column operation Nov 10, 2021 Issued
Array ( [id] => 18593092 [patent_doc_number] => 11742000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Circuit module with improved line load [patent_app_type] => utility [patent_app_number] => 17/521894 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521894
Circuit module with improved line load Nov 8, 2021 Issued
Array ( [id] => 18347608 [patent_doc_number] => 20230135718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => REGULATOR CIRCUIT AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/518797 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518797
Regulator circuit and methods thereof Nov 3, 2021 Issued
Array ( [id] => 18645484 [patent_doc_number] => 11769562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Semiconductor device including an electronic fuse control circuit [patent_app_type] => utility [patent_app_number] => 17/517794 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7029 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517794
Semiconductor device including an electronic fuse control circuit Nov 2, 2021 Issued
Array ( [id] => 17431828 [patent_doc_number] => 20220059537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Semiconductor Memory Device Having an Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 17/517570 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517570
Semiconductor memory device having an electrically floating body transistor Nov 1, 2021 Issued
Array ( [id] => 17507307 [patent_doc_number] => 20220100410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CIRCUIT FOR TESTING A MEMORY AND TEST METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/510457 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510457 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510457
Circuit for testing a memory and test method thereof Oct 25, 2021 Issued
Array ( [id] => 18155915 [patent_doc_number] => 11568904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Memory with positively boosted write multiplexer [patent_app_type] => utility [patent_app_number] => 17/451110 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6584 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451110
Memory with positively boosted write multiplexer Oct 14, 2021 Issued
Array ( [id] => 18137093 [patent_doc_number] => 11562781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-24 [patent_title] => Memory devices with low pin count interfaces, and corresponding methods and systems [patent_app_type] => utility [patent_app_number] => 17/499938 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 54 [patent_no_of_words] => 11768 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499938
Memory devices with low pin count interfaces, and corresponding methods and systems Oct 12, 2021 Issued
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