
Huan Hoang
Examiner (ID: 18810, Phone: (571)272-1779 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2154, 2827, 2511 |
| Total Applications | 3293 |
| Issued Applications | 3069 |
| Pending Applications | 116 |
| Abandoned Applications | 129 |
Applications
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|---|---|---|---|
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