
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3809468
[patent_doc_number] => 05828618
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Line memory'
[patent_app_type] => 1
[patent_app_number] => 8/895908
[patent_app_country] => US
[patent_app_date] => 1997-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
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[pdf_file] => patents/05/828/05828618.pdf
[firstpage_image] =>[orig_patent_app_number] => 895908
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895908 | Line memory | Jul 16, 1997 | Issued |
Array
(
[id] => 3889259
[patent_doc_number] => 05825682
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Cache memory capable of using faulty tag memory'
[patent_app_type] => 1
[patent_app_number] => 8/895206
[patent_app_country] => US
[patent_app_date] => 1997-07-16
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[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/05/825/05825682.pdf
[firstpage_image] =>[orig_patent_app_number] => 895206
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895206 | Cache memory capable of using faulty tag memory | Jul 15, 1997 | Issued |
Array
(
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[patent_doc_number] => 05812472
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Nested loop method of identifying synchronous memories'
[patent_app_type] => 1
[patent_app_number] => 8/895305
[patent_app_country] => US
[patent_app_date] => 1997-07-16
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[patent_drawing_sheets_cnt] => 48
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[firstpage_image] =>[orig_patent_app_number] => 895305
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895305 | Nested loop method of identifying synchronous memories | Jul 15, 1997 | Issued |
Array
(
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[patent_doc_number] => 05995424
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Synchronous memory test system'
[patent_app_type] => 1
[patent_app_number] => 8/895307
[patent_app_country] => US
[patent_app_date] => 1997-07-16
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[firstpage_image] =>[orig_patent_app_number] => 895307
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895307 | Synchronous memory test system | Jul 15, 1997 | Issued |
Array
(
[id] => 3789991
[patent_doc_number] => 05757697
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Method for sensing the binary state of a floating-gate memory device'
[patent_app_type] => 1
[patent_app_number] => 8/893282
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[pdf_file] => patents/05/757/05757697.pdf
[firstpage_image] =>[orig_patent_app_number] => 893282
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893282 | Method for sensing the binary state of a floating-gate memory device | Jul 14, 1997 | Issued |
Array
(
[id] => 4026951
[patent_doc_number] => 05880987
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Architecture and package orientation for high speed memory devices'
[patent_app_type] => 1
[patent_app_number] => 8/892607
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[pdf_file] => patents/05/880/05880987.pdf
[firstpage_image] =>[orig_patent_app_number] => 892607
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/892607 | Architecture and package orientation for high speed memory devices | Jul 13, 1997 | Issued |
Array
(
[id] => 3845371
[patent_doc_number] => 05815428
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Semiconductor memory device having hierarchical bit line structure'
[patent_app_type] => 1
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[patent_app_date] => 1997-07-14
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[pdf_file] => patents/05/815/05815428.pdf
[firstpage_image] =>[orig_patent_app_number] => 893045
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893045 | Semiconductor memory device having hierarchical bit line structure | Jul 13, 1997 | Issued |
Array
(
[id] => 3797878
[patent_doc_number] => 05822239
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Method of writing data to a single transistor type ferroelectric memory'
[patent_app_type] => 1
[patent_app_number] => 8/891157
[patent_app_country] => US
[patent_app_date] => 1997-07-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/822/05822239.pdf
[firstpage_image] =>[orig_patent_app_number] => 891157
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/891157 | Method of writing data to a single transistor type ferroelectric memory | Jul 9, 1997 | Issued |
Array
(
[id] => 3993647
[patent_doc_number] => 05949696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Differential dynamic content addressable memory and high speed network address filtering'
[patent_app_type] => 1
[patent_app_number] => 8/885909
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[patent_app_date] => 1997-06-30
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[pdf_file] => patents/05/949/05949696.pdf
[firstpage_image] =>[orig_patent_app_number] => 885909
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/885909 | Differential dynamic content addressable memory and high speed network address filtering | Jun 29, 1997 | Issued |
Array
(
[id] => 4027163
[patent_doc_number] => 05880999
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Read only/random access memory architecture and methods for operating same'
[patent_app_type] => 1
[patent_app_number] => 8/884561
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[pdf_file] => patents/05/880/05880999.pdf
[firstpage_image] =>[orig_patent_app_number] => 884561
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/884561 | Read only/random access memory architecture and methods for operating same | Jun 26, 1997 | Issued |
Array
(
[id] => 3957305
[patent_doc_number] => 05982678
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Semiconductor memory device with redundancy circuit'
[patent_app_type] => 1
[patent_app_number] => 8/882758
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[pdf_file] => patents/05/982/05982678.pdf
[firstpage_image] =>[orig_patent_app_number] => 882758
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/882758 | Semiconductor memory device with redundancy circuit | Jun 25, 1997 | Issued |
Array
(
[id] => 3915163
[patent_doc_number] => 05898613
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'pMOS analog EEPROM cell'
[patent_app_type] => 1
[patent_app_number] => 8/882717
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[pdf_file] => patents/05/898/05898613.pdf
[firstpage_image] =>[orig_patent_app_number] => 882717
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/882717 | pMOS analog EEPROM cell | Jun 24, 1997 | Issued |
Array
(
[id] => 4073024
[patent_doc_number] => 05896309
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[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Semiconductor-on-insulator transistor, memory circuitry employing semiconductor-on-insulator transistors, method of forming a semiconductor-on-insulator transistor, and method of forming memory circuitry employing semiconductor-on-insulator transistors'
[patent_app_type] => 1
[patent_app_number] => 8/881559
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[firstpage_image] =>[orig_patent_app_number] => 881559
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881559 | Semiconductor-on-insulator transistor, memory circuitry employing semiconductor-on-insulator transistors, method of forming a semiconductor-on-insulator transistor, and method of forming memory circuitry employing semiconductor-on-insulator transistors | Jun 23, 1997 | Abandoned |
Array
(
[id] => 3939804
[patent_doc_number] => 05877985
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[patent_issue_date] => 1999-03-02
[patent_title] => 'Intermediate voltage generating circuit and nonvolatile semiconductor memory having the same'
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Array
(
[id] => 3756777
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[patent_title] => 'Ping-pong boost circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881603 | Ping-pong boost circuit | Jun 23, 1997 | Issued |
Array
(
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[patent_title] => 'Variable voltage isolation gate and method'
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Array
(
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[patent_title] => 'Boost voltage generator for controlling a memory cell array'
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Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/864506 | Method and apparatus for transferring data in a dual port memory | May 27, 1997 | Issued |