Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3809468 [patent_doc_number] => 05828618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Line memory' [patent_app_type] => 1 [patent_app_number] => 8/895908 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4621 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828618.pdf [firstpage_image] =>[orig_patent_app_number] => 895908 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895908
Line memory Jul 16, 1997 Issued
Array ( [id] => 3889259 [patent_doc_number] => 05825682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Cache memory capable of using faulty tag memory' [patent_app_type] => 1 [patent_app_number] => 8/895206 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4246 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825682.pdf [firstpage_image] =>[orig_patent_app_number] => 895206 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895206
Cache memory capable of using faulty tag memory Jul 15, 1997 Issued
Array ( [id] => 3825093 [patent_doc_number] => 05812472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Nested loop method of identifying synchronous memories' [patent_app_type] => 1 [patent_app_number] => 8/895305 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 31273 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812472.pdf [firstpage_image] =>[orig_patent_app_number] => 895305 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895305
Nested loop method of identifying synchronous memories Jul 15, 1997 Issued
Array ( [id] => 4047947 [patent_doc_number] => 05995424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Synchronous memory test system' [patent_app_type] => 1 [patent_app_number] => 8/895307 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 31212 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995424.pdf [firstpage_image] =>[orig_patent_app_number] => 895307 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895307
Synchronous memory test system Jul 15, 1997 Issued
Array ( [id] => 3789991 [patent_doc_number] => 05757697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Method for sensing the binary state of a floating-gate memory device' [patent_app_type] => 1 [patent_app_number] => 8/893282 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4207 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757697.pdf [firstpage_image] =>[orig_patent_app_number] => 893282 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893282
Method for sensing the binary state of a floating-gate memory device Jul 14, 1997 Issued
Array ( [id] => 4026951 [patent_doc_number] => 05880987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Architecture and package orientation for high speed memory devices' [patent_app_type] => 1 [patent_app_number] => 8/892607 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5363 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880987.pdf [firstpage_image] =>[orig_patent_app_number] => 892607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892607
Architecture and package orientation for high speed memory devices Jul 13, 1997 Issued
Array ( [id] => 3845371 [patent_doc_number] => 05815428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Semiconductor memory device having hierarchical bit line structure' [patent_app_type] => 1 [patent_app_number] => 8/893045 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6936 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815428.pdf [firstpage_image] =>[orig_patent_app_number] => 893045 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893045
Semiconductor memory device having hierarchical bit line structure Jul 13, 1997 Issued
Array ( [id] => 3797878 [patent_doc_number] => 05822239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method of writing data to a single transistor type ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 8/891157 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2957 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822239.pdf [firstpage_image] =>[orig_patent_app_number] => 891157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891157
Method of writing data to a single transistor type ferroelectric memory Jul 9, 1997 Issued
Array ( [id] => 3993647 [patent_doc_number] => 05949696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Differential dynamic content addressable memory and high speed network address filtering' [patent_app_type] => 1 [patent_app_number] => 8/885909 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5702 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949696.pdf [firstpage_image] =>[orig_patent_app_number] => 885909 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885909
Differential dynamic content addressable memory and high speed network address filtering Jun 29, 1997 Issued
Array ( [id] => 4027163 [patent_doc_number] => 05880999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Read only/random access memory architecture and methods for operating same' [patent_app_type] => 1 [patent_app_number] => 8/884561 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6209 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880999.pdf [firstpage_image] =>[orig_patent_app_number] => 884561 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884561
Read only/random access memory architecture and methods for operating same Jun 26, 1997 Issued
Array ( [id] => 3957305 [patent_doc_number] => 05982678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor memory device with redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 8/882758 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 5202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982678.pdf [firstpage_image] =>[orig_patent_app_number] => 882758 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882758
Semiconductor memory device with redundancy circuit Jun 25, 1997 Issued
Array ( [id] => 3915163 [patent_doc_number] => 05898613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'pMOS analog EEPROM cell' [patent_app_type] => 1 [patent_app_number] => 8/882717 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 6580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898613.pdf [firstpage_image] =>[orig_patent_app_number] => 882717 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882717
pMOS analog EEPROM cell Jun 24, 1997 Issued
Array ( [id] => 4073024 [patent_doc_number] => 05896309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Semiconductor-on-insulator transistor, memory circuitry employing semiconductor-on-insulator transistors, method of forming a semiconductor-on-insulator transistor, and method of forming memory circuitry employing semiconductor-on-insulator transistors' [patent_app_type] => 1 [patent_app_number] => 8/881559 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3200 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896309.pdf [firstpage_image] =>[orig_patent_app_number] => 881559 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881559
Semiconductor-on-insulator transistor, memory circuitry employing semiconductor-on-insulator transistors, method of forming a semiconductor-on-insulator transistor, and method of forming memory circuitry employing semiconductor-on-insulator transistors Jun 23, 1997 Abandoned
Array ( [id] => 3939804 [patent_doc_number] => 05877985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Intermediate voltage generating circuit and nonvolatile semiconductor memory having the same' [patent_app_type] => 1 [patent_app_number] => 8/881061 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 17875 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877985.pdf [firstpage_image] =>[orig_patent_app_number] => 881061 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881061
Intermediate voltage generating circuit and nonvolatile semiconductor memory having the same Jun 23, 1997 Issued
Array ( [id] => 3756777 [patent_doc_number] => 05801997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Ping-pong boost circuit' [patent_app_type] => 1 [patent_app_number] => 8/881603 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3777 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801997.pdf [firstpage_image] =>[orig_patent_app_number] => 881603 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881603
Ping-pong boost circuit Jun 23, 1997 Issued
Array ( [id] => 3970830 [patent_doc_number] => 05901078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Variable voltage isolation gate and method' [patent_app_type] => 1 [patent_app_number] => 8/878657 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2620 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901078.pdf [firstpage_image] =>[orig_patent_app_number] => 878657 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878657
Variable voltage isolation gate and method Jun 18, 1997 Issued
Array ( [id] => 3980660 [patent_doc_number] => 05886933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Boost voltage generator for controlling a memory cell array' [patent_app_type] => 1 [patent_app_number] => 8/879757 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2382 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886933.pdf [firstpage_image] =>[orig_patent_app_number] => 879757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879757
Boost voltage generator for controlling a memory cell array Jun 18, 1997 Issued
Array ( [id] => 4027421 [patent_doc_number] => 05881016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method and apparatus for optimizing power consumption and memory bandwidth in a video controller using SGRAM and SDRAM power reduction modes' [patent_app_type] => 1 [patent_app_number] => 8/874657 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6441 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881016.pdf [firstpage_image] =>[orig_patent_app_number] => 874657 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874657
Method and apparatus for optimizing power consumption and memory bandwidth in a video controller using SGRAM and SDRAM power reduction modes Jun 12, 1997 Issued
Array ( [id] => 3821282 [patent_doc_number] => 05831909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Memory device tracking circuit' [patent_app_type] => 1 [patent_app_number] => 8/872081 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3099 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831909.pdf [firstpage_image] =>[orig_patent_app_number] => 872081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872081
Memory device tracking circuit Jun 9, 1997 Issued
Array ( [id] => 1426295 [patent_doc_number] => 06510098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method and apparatus for transferring data in a dual port memory' [patent_app_type] => B1 [patent_app_number] => 08/864506 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6306 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510098.pdf [firstpage_image] =>[orig_patent_app_number] => 08864506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864506
Method and apparatus for transferring data in a dual port memory May 27, 1997 Issued
Menu