
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3809306
[patent_doc_number] => 05828607
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Memory programming circuit and method'
[patent_app_type] => 1
[patent_app_number] => 8/861078
[patent_app_country] => US
[patent_app_date] => 1997-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 6697
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/828/05828607.pdf
[firstpage_image] =>[orig_patent_app_number] => 861078
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/861078 | Memory programming circuit and method | May 20, 1997 | Issued |
Array
(
[id] => 4061354
[patent_doc_number] => 05870350
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'High performance, high bandwidth memory bus architecture utilizing SDRAMs'
[patent_app_type] => 1
[patent_app_number] => 8/861101
[patent_app_country] => US
[patent_app_date] => 1997-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 1849
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 261
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/870/05870350.pdf
[firstpage_image] =>[orig_patent_app_number] => 861101
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/861101 | High performance, high bandwidth memory bus architecture utilizing SDRAMs | May 20, 1997 | Issued |
Array
(
[id] => 3845383
[patent_doc_number] => 05815429
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Antifuse programming method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/858945
[patent_app_country] => US
[patent_app_date] => 1997-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3683
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/815/05815429.pdf
[firstpage_image] =>[orig_patent_app_number] => 858945
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/858945 | Antifuse programming method and apparatus | May 19, 1997 | Issued |
Array
(
[id] => 4005371
[patent_doc_number] => 05920519
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Semiconductor memory with sensing stability'
[patent_app_type] => 1
[patent_app_number] => 8/855256
[patent_app_country] => US
[patent_app_date] => 1997-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 2700
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/920/05920519.pdf
[firstpage_image] =>[orig_patent_app_number] => 855256
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/855256 | Semiconductor memory with sensing stability | May 12, 1997 | Issued |
Array
(
[id] => 4004894
[patent_doc_number] => 05892709
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Single level gate nonvolatile memory device and method for accessing the same'
[patent_app_type] => 1
[patent_app_number] => 8/853601
[patent_app_country] => US
[patent_app_date] => 1997-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 7108
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/892/05892709.pdf
[firstpage_image] =>[orig_patent_app_number] => 853601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/853601 | Single level gate nonvolatile memory device and method for accessing the same | May 8, 1997 | Issued |
Array
(
[id] => 3891993
[patent_doc_number] => 05805494
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Trench capacitor structures'
[patent_app_type] => 1
[patent_app_number] => 8/846603
[patent_app_country] => US
[patent_app_date] => 1997-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4015
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805494.pdf
[firstpage_image] =>[orig_patent_app_number] => 846603
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/846603 | Trench capacitor structures | Apr 29, 1997 | Issued |
Array
(
[id] => 4010706
[patent_doc_number] => 05923599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Apparatus and method for subarray testing in dynamic random access memories using a built-in-self-test unit'
[patent_app_type] => 1
[patent_app_number] => 8/840362
[patent_app_country] => US
[patent_app_date] => 1997-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1810
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/923/05923599.pdf
[firstpage_image] =>[orig_patent_app_number] => 840362
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840362 | Apparatus and method for subarray testing in dynamic random access memories using a built-in-self-test unit | Apr 28, 1997 | Issued |
Array
(
[id] => 4004946
[patent_doc_number] => 05892712
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Semiconductor non-volatile latch device including embedded non-volatile elements'
[patent_app_type] => 1
[patent_app_number] => 8/846558
[patent_app_country] => US
[patent_app_date] => 1997-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 14396
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/892/05892712.pdf
[firstpage_image] =>[orig_patent_app_number] => 846558
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/846558 | Semiconductor non-volatile latch device including embedded non-volatile elements | Apr 28, 1997 | Issued |
Array
(
[id] => 3802272
[patent_doc_number] => 05841693
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Non-volatile memory using field effect transistors having dual floating gates for storing two bits per cell'
[patent_app_type] => 1
[patent_app_number] => 8/840698
[patent_app_country] => US
[patent_app_date] => 1997-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 2547
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841693.pdf
[firstpage_image] =>[orig_patent_app_number] => 840698
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840698 | Non-volatile memory using field effect transistors having dual floating gates for storing two bits per cell | Apr 24, 1997 | Issued |
Array
(
[id] => 4004867
[patent_doc_number] => 05892707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Memory array having a digit line buried in an isolation region and method for forming same'
[patent_app_type] => 1
[patent_app_number] => 8/845609
[patent_app_country] => US
[patent_app_date] => 1997-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 39
[patent_no_of_words] => 6333
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/892/05892707.pdf
[firstpage_image] =>[orig_patent_app_number] => 845609
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/845609 | Memory array having a digit line buried in an isolation region and method for forming same | Apr 24, 1997 | Issued |
Array
(
[id] => 4045537
[patent_doc_number] => 05856939
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'Low voltage dynamic memory'
[patent_app_type] => 1
[patent_app_number] => 8/840599
[patent_app_country] => US
[patent_app_date] => 1997-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3709
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/856/05856939.pdf
[firstpage_image] =>[orig_patent_app_number] => 840599
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840599 | Low voltage dynamic memory | Apr 21, 1997 | Issued |
Array
(
[id] => 3915372
[patent_doc_number] => 05898628
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Data transfer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/842903
[patent_app_country] => US
[patent_app_date] => 1997-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3454
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/898/05898628.pdf
[firstpage_image] =>[orig_patent_app_number] => 842903
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/842903 | Data transfer circuit | Apr 16, 1997 | Issued |
Array
(
[id] => 3948677
[patent_doc_number] => 05872739
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Sense amplifier for low read-voltage memory cells'
[patent_app_type] => 1
[patent_app_number] => 8/841905
[patent_app_country] => US
[patent_app_date] => 1997-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2511
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/872/05872739.pdf
[firstpage_image] =>[orig_patent_app_number] => 841905
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/841905 | Sense amplifier for low read-voltage memory cells | Apr 16, 1997 | Issued |
Array
(
[id] => 3962271
[patent_doc_number] => 05956277
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Circuit and method for performing tests on memory array cells using external sense amplifier reference current'
[patent_app_type] => 1
[patent_app_number] => 8/843520
[patent_app_country] => US
[patent_app_date] => 1997-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 11989
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/956/05956277.pdf
[firstpage_image] =>[orig_patent_app_number] => 843520
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/843520 | Circuit and method for performing tests on memory array cells using external sense amplifier reference current | Apr 15, 1997 | Issued |
Array
(
[id] => 3804541
[patent_doc_number] => 05726940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'Semiconductor memory device of which prescribed state of operation is terminated under a prescribed condition and method of operating a semiconductor memory device for terminating prescribed state of operation'
[patent_app_type] => 1
[patent_app_number] => 8/833207
[patent_app_country] => US
[patent_app_date] => 1997-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 4958
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/726/05726940.pdf
[firstpage_image] =>[orig_patent_app_number] => 833207
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/833207 | Semiconductor memory device of which prescribed state of operation is terminated under a prescribed condition and method of operating a semiconductor memory device for terminating prescribed state of operation | Apr 13, 1997 | Issued |
Array
(
[id] => 4073113
[patent_doc_number] => 05896315
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Nonvolatile memory'
[patent_app_type] => 1
[patent_app_number] => 8/840303
[patent_app_country] => US
[patent_app_date] => 1997-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4644
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/896/05896315.pdf
[firstpage_image] =>[orig_patent_app_number] => 840303
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840303 | Nonvolatile memory | Apr 10, 1997 | Issued |
| 08/840154 | SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE IN WHICH CURRENT CONSUMED BY INPUT BUFFER CIRCUIT IS REDUCED | Apr 10, 1997 | Abandoned |
Array
(
[id] => 3905141
[patent_doc_number] => 05835423
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 8/838508
[patent_app_country] => US
[patent_app_date] => 1997-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 4883
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/835/05835423.pdf
[firstpage_image] =>[orig_patent_app_number] => 838508
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/838508 | Semiconductor memory | Apr 7, 1997 | Issued |
Array
(
[id] => 3980859
[patent_doc_number] => 05886946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Semiconductor memory device allowing reduction in power consumption during standby'
[patent_app_type] => 1
[patent_app_number] => 8/833479
[patent_app_country] => US
[patent_app_date] => 1997-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 52
[patent_no_of_words] => 22908
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/886/05886946.pdf
[firstpage_image] =>[orig_patent_app_number] => 833479
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/833479 | Semiconductor memory device allowing reduction in power consumption during standby | Apr 6, 1997 | Issued |
Array
(
[id] => 3971244
[patent_doc_number] => 05901103
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Integrated circuit having standby control for memory and method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/835363
[patent_app_country] => US
[patent_app_date] => 1997-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6756
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/901/05901103.pdf
[firstpage_image] =>[orig_patent_app_number] => 835363
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/835363 | Integrated circuit having standby control for memory and method thereof | Apr 6, 1997 | Issued |