
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3882887
[patent_doc_number] => 05838615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Nonvolatile semiconductor memory device having reduced source line resistance'
[patent_app_type] => 1
[patent_app_number] => 8/795018
[patent_app_country] => US
[patent_app_date] => 1997-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4222
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/838/05838615.pdf
[firstpage_image] =>[orig_patent_app_number] => 795018
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/795018 | Nonvolatile semiconductor memory device having reduced source line resistance | Feb 4, 1997 | Issued |
Array
(
[id] => 3897705
[patent_doc_number] => 05715198
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Output latching circuit for static memory devices'
[patent_app_type] => 1
[patent_app_number] => 8/792030
[patent_app_country] => US
[patent_app_date] => 1997-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1677
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/715/05715198.pdf
[firstpage_image] =>[orig_patent_app_number] => 792030
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/792030 | Output latching circuit for static memory devices | Feb 2, 1997 | Issued |
Array
(
[id] => 3798069
[patent_doc_number] => 05822254
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Synchronous semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/791034
[patent_app_country] => US
[patent_app_date] => 1997-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3776
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822254.pdf
[firstpage_image] =>[orig_patent_app_number] => 791034
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/791034 | Synchronous semiconductor memory device | Jan 28, 1997 | Issued |
Array
(
[id] => 3852083
[patent_doc_number] => 05708617
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Regressive drive sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/790377
[patent_app_country] => US
[patent_app_date] => 1997-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5869
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/708/05708617.pdf
[firstpage_image] =>[orig_patent_app_number] => 790377
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/790377 | Regressive drive sense amplifier | Jan 27, 1997 | Issued |
Array
(
[id] => 3913221
[patent_doc_number] => 05751657
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/788933
[patent_app_country] => US
[patent_app_date] => 1997-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7352
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 272
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751657.pdf
[firstpage_image] =>[orig_patent_app_number] => 788933
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/788933 | Semiconductor memory device | Jan 23, 1997 | Issued |
Array
(
[id] => 3739229
[patent_doc_number] => 05703822
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Serial access memory device including memory sections having different latencies'
[patent_app_type] => 1
[patent_app_number] => 8/788077
[patent_app_country] => US
[patent_app_date] => 1997-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 38
[patent_no_of_words] => 5783
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/703/05703822.pdf
[firstpage_image] =>[orig_patent_app_number] => 788077
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/788077 | Serial access memory device including memory sections having different latencies | Jan 21, 1997 | Issued |
Array
(
[id] => 3873624
[patent_doc_number] => 05793671
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Static random access memory cell utilizing enhancement mode N-channel transistors as load elements'
[patent_app_type] => 1
[patent_app_number] => 8/786428
[patent_app_country] => US
[patent_app_date] => 1997-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3625
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/793/05793671.pdf
[firstpage_image] =>[orig_patent_app_number] => 786428
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/786428 | Static random access memory cell utilizing enhancement mode N-channel transistors as load elements | Jan 20, 1997 | Issued |
Array
(
[id] => 3889670
[patent_doc_number] => 05825709
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/783032
[patent_app_country] => US
[patent_app_date] => 1997-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5165
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825709.pdf
[firstpage_image] =>[orig_patent_app_number] => 783032
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/783032 | Semiconductor memory device | Jan 13, 1997 | Issued |
Array
(
[id] => 3756815
[patent_doc_number] => 05717639
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Memory device having circuitry for initializing and reprogramming a control operation feature'
[patent_app_type] => 1
[patent_app_number] => 8/783380
[patent_app_country] => US
[patent_app_date] => 1997-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 7154
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717639.pdf
[firstpage_image] =>[orig_patent_app_number] => 783380
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/783380 | Memory device having circuitry for initializing and reprogramming a control operation feature | Jan 12, 1997 | Issued |
Array
(
[id] => 3853942
[patent_doc_number] => 05848024
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Clock controlled column decoder'
[patent_app_type] => 1
[patent_app_number] => 8/780632
[patent_app_country] => US
[patent_app_date] => 1997-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4561
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/848/05848024.pdf
[firstpage_image] =>[orig_patent_app_number] => 780632
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/780632 | Clock controlled column decoder | Jan 7, 1997 | Issued |
Array
(
[id] => 3867566
[patent_doc_number] => 05706226
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Low voltage CMOS SRAM'
[patent_app_type] => 1
[patent_app_number] => 8/777778
[patent_app_country] => US
[patent_app_date] => 1996-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4636
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/706/05706226.pdf
[firstpage_image] =>[orig_patent_app_number] => 777778
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777778 | Low voltage CMOS SRAM | Dec 30, 1996 | Issued |
Array
(
[id] => 3798165
[patent_doc_number] => 05822261
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Semiconductor memory device with increased bandwidth'
[patent_app_type] => 1
[patent_app_number] => 8/777178
[patent_app_country] => US
[patent_app_date] => 1996-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 4248
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[patent_no_of_ind_claims] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822261.pdf
[firstpage_image] =>[orig_patent_app_number] => 777178
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777178 | Semiconductor memory device with increased bandwidth | Dec 26, 1996 | Issued |
Array
(
[id] => 3780112
[patent_doc_number] => 05850365
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Sense amplifier with individually optimized high and low power modes'
[patent_app_type] => 1
[patent_app_number] => 8/772567
[patent_app_country] => US
[patent_app_date] => 1996-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 13454
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 6
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/850/05850365.pdf
[firstpage_image] =>[orig_patent_app_number] => 772567
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/772567 | Sense amplifier with individually optimized high and low power modes | Dec 23, 1996 | Issued |
Array
(
[id] => 3798293
[patent_doc_number] => 05822270
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Circuit for generating internal column address suitable for burst mode'
[patent_app_type] => 1
[patent_app_number] => 8/769434
[patent_app_country] => US
[patent_app_date] => 1996-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 3489
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[patent_words_short_claim] => 151
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822270.pdf
[firstpage_image] =>[orig_patent_app_number] => 769434
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/769434 | Circuit for generating internal column address suitable for burst mode | Dec 18, 1996 | Issued |
Array
(
[id] => 3891905
[patent_doc_number] => 05798976
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Semiconductor memory device with reduced current consumption in data holding mode'
[patent_app_type] => 1
[patent_app_number] => 8/768078
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/798/05798976.pdf
[firstpage_image] =>[orig_patent_app_number] => 768078
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768078 | Semiconductor memory device with reduced current consumption in data holding mode | Dec 15, 1996 | Issued |
Array
(
[id] => 3698198
[patent_doc_number] => 05691954
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Semiconductor memory device in which data are read and written asynchronously with application of address signal'
[patent_app_type] => 1
[patent_app_number] => 8/768077
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[pdf_file] => patents/05/691/05691954.pdf
[firstpage_image] =>[orig_patent_app_number] => 768077
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768077 | Semiconductor memory device in which data are read and written asynchronously with application of address signal | Dec 15, 1996 | Issued |
Array
(
[id] => 3804658
[patent_doc_number] => 05726948
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'Multi-port memory device with multiple sets of columns'
[patent_app_type] => 1
[patent_app_number] => 8/761233
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/726/05726948.pdf
[firstpage_image] =>[orig_patent_app_number] => 761233
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761233 | Multi-port memory device with multiple sets of columns | Dec 5, 1996 | Issued |
Array
(
[id] => 3733365
[patent_doc_number] => 05701266
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'Programming flash memory using distributed learning methods'
[patent_app_type] => 1
[patent_app_number] => 8/760928
[patent_app_country] => US
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[pdf_file] => patents/05/701/05701266.pdf
[firstpage_image] =>[orig_patent_app_number] => 760928
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760928 | Programming flash memory using distributed learning methods | Dec 5, 1996 | Issued |
Array
(
[id] => 3853803
[patent_doc_number] => 05745414
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Integrated circuit system having reference cells for improving the reading of storage cells'
[patent_app_type] => 1
[patent_app_number] => 8/756564
[patent_app_country] => US
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[pdf_file] => patents/05/745/05745414.pdf
[firstpage_image] =>[orig_patent_app_number] => 756564
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756564 | Integrated circuit system having reference cells for improving the reading of storage cells | Nov 25, 1996 | Issued |
Array
(
[id] => 3753183
[patent_doc_number] => 05754470
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Apparatus for programming a voltage within a storage element'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754470.pdf
[firstpage_image] =>[orig_patent_app_number] => 756567
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756567 | Apparatus for programming a voltage within a storage element | Nov 25, 1996 | Issued |