Huan Hoang

Array ( [id] => 3830436 [patent_doc_number] => 05790450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Semiconductor memory device having bit lines widely spaced without sacrifice of narrow pitch of source/drain lines of memory cells' [patent_app_type] => 1 [patent_app_number] => 8/730677 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10842 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 593 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790450.pdf [firstpage_image] =>[orig_patent_app_number] => 730677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3888877 [patent_doc_number] => 05764586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Intermediate size non-volatile electrically alterable semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/729009 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8063 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764586.pdf [firstpage_image] =>[orig_patent_app_number] => 729009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3809115 [patent_doc_number] => 05828595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Optical recording and playback apparatus and method using single light absorbents' [patent_app_type] => 1 [patent_app_number] => 8/729301 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4174 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828595.pdf [firstpage_image] =>[orig_patent_app_number] => 729301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3752155 [patent_doc_number] => 05787041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'System and method for improving a random access memory (RAM)' [patent_app_type] => 1 [patent_app_number] => 8/724204 [patent_app_country] => US [patent_app_date] => 1996-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4976 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787041.pdf [firstpage_image] =>[orig_patent_app_number] => 724204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3888572 [patent_doc_number] => 05764563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Thin film load structure' [patent_app_type] => 1 [patent_app_number] => 8/723007 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5317 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764563.pdf [firstpage_image] =>[orig_patent_app_number] => 723007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3807706 [patent_doc_number] => 05781474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Parallel programming method of memory words and corresponding circuit' [patent_app_type] => 1 [patent_app_number] => 8/722378 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781474.pdf [firstpage_image] =>[orig_patent_app_number] => 722378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867216 [patent_doc_number] => 05768215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Integrated circuit memory devices having interleaved read capability and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 8/722478 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10636 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768215.pdf [firstpage_image] =>[orig_patent_app_number] => 722478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836245 [patent_doc_number] => 05732035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Very large scale integrated planar read only memory' [patent_app_type] => 1 [patent_app_number] => 8/721342 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 39 [patent_no_of_words] => 28944 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732035.pdf [firstpage_image] =>[orig_patent_app_number] => 721342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054417 [patent_doc_number] => 05875126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Autozeroing floating gate amplifier' [patent_app_type] => 1 [patent_app_number] => 8/721261 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 13196 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875126.pdf [firstpage_image] =>[orig_patent_app_number] => 721261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3858414 [patent_doc_number] => 05719814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Semiconductor memory device capable of storing high potential level of data' [patent_app_type] => 1 [patent_app_number] => 8/719880 [patent_app_country] => US [patent_app_date] => 1996-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 7281 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719814.pdf [firstpage_image] =>[orig_patent_app_number] => 719880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3851872 [patent_doc_number] => 05708605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Nonvolatile semiconductor memory device having variable writing and erasing time periods' [patent_app_type] => 1 [patent_app_number] => 8/719980 [patent_app_country] => US [patent_app_date] => 1996-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 3493 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708605.pdf [firstpage_image] =>[orig_patent_app_number] => 719980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3891786 [patent_doc_number] => 05798968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Plane decode/virtual sector architecture' [patent_app_type] => 1 [patent_app_number] => 8/719179 [patent_app_country] => US [patent_app_date] => 1996-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 9096 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798968.pdf [firstpage_image] =>[orig_patent_app_number] => 719179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3772530 [patent_doc_number] => 05742557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Multi-port random access memory' [patent_app_type] => 1 [patent_app_number] => 8/719306 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12819 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742557.pdf [firstpage_image] =>[orig_patent_app_number] => 719306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3780854 [patent_doc_number] => 05734613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Multi-port random access memory' [patent_app_type] => 1 [patent_app_number] => 8/719301 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12851 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734613.pdf [firstpage_image] =>[orig_patent_app_number] => 719301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3830657 [patent_doc_number] => 05790465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Wafer burn-in test circuit and a method thereof' [patent_app_type] => 1 [patent_app_number] => 8/714577 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2077 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790465.pdf [firstpage_image] =>[orig_patent_app_number] => 714577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867105 [patent_doc_number] => 05768207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Power-up circuit responsive to supply voltage transients' [patent_app_type] => 1 [patent_app_number] => 8/706719 [patent_app_country] => US [patent_app_date] => 1996-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4058 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768207.pdf [firstpage_image] =>[orig_patent_app_number] => 706719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3715986 [patent_doc_number] => 05654930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Semiconductor memory device having low power self refresh and burn-in functions' [patent_app_type] => 1 [patent_app_number] => 8/705040 [patent_app_country] => US [patent_app_date] => 1996-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6977 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654930.pdf [firstpage_image] =>[orig_patent_app_number] => 705040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3629612 [patent_doc_number] => 05642314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/706196 [patent_app_country] => US [patent_app_date] => 1996-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 7213 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642314.pdf [firstpage_image] =>[orig_patent_app_number] => 706196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853664 [patent_doc_number] => 05745405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Process leakage evaluation and measurement method' [patent_app_type] => 1 [patent_app_number] => 8/703078 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2062 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 508 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745405.pdf [firstpage_image] =>[orig_patent_app_number] => 703078 [rel_patent_id] =>[rel_patent_doc_number] =>)