
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3631113
[patent_doc_number] => 05689465
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'Semiconductor memory device and defective memory cell correction circuit'
[patent_app_type] => 1
[patent_app_number] => 8/703178
[patent_app_country] => US
[patent_app_date] => 1996-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 39
[patent_no_of_words] => 13587
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/689/05689465.pdf
[firstpage_image] =>[orig_patent_app_number] => 703178
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/703178 | Semiconductor memory device and defective memory cell correction circuit | Aug 25, 1996 | Issued |
Array
(
[id] => 3739352
[patent_doc_number] => 05703830
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Syncronous dynamic semiconductor memory device using pipelined multi-bit prefetch architecture'
[patent_app_type] => 1
[patent_app_number] => 8/701879
[patent_app_country] => US
[patent_app_date] => 1996-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 40
[patent_no_of_words] => 3158
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/703/05703830.pdf
[firstpage_image] =>[orig_patent_app_number] => 701879
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/701879 | Syncronous dynamic semiconductor memory device using pipelined multi-bit prefetch architecture | Aug 22, 1996 | Issued |
Array
(
[id] => 3853596
[patent_doc_number] => 05848002
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Information storage apparatus and method for operating the same'
[patent_app_type] => 1
[patent_app_number] => 8/696879
[patent_app_country] => US
[patent_app_date] => 1996-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 116
[patent_no_of_words] => 17890
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/848/05848002.pdf
[firstpage_image] =>[orig_patent_app_number] => 696879
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/696879 | Information storage apparatus and method for operating the same | Aug 19, 1996 | Issued |
Array
(
[id] => 3747201
[patent_doc_number] => 05699291
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Semiconductor memory device and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/690779
[patent_app_country] => US
[patent_app_date] => 1996-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 19
[patent_no_of_words] => 7246
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/699/05699291.pdf
[firstpage_image] =>[orig_patent_app_number] => 690779
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/690779 | Semiconductor memory device and manufacturing method thereof | Jul 31, 1996 | Issued |
Array
(
[id] => 3674131
[patent_doc_number] => 05668751
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'Antifuse programming method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/690777
[patent_app_country] => US
[patent_app_date] => 1996-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3684
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/668/05668751.pdf
[firstpage_image] =>[orig_patent_app_number] => 690777
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/690777 | Antifuse programming method and apparatus | Jul 31, 1996 | Issued |
Array
(
[id] => 3853903
[patent_doc_number] => 05745419
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Method and apparatus for measuring the offset voltages of SRAM sense amplifiers'
[patent_app_type] => 1
[patent_app_number] => 8/690631
[patent_app_country] => US
[patent_app_date] => 1996-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4296
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/745/05745419.pdf
[firstpage_image] =>[orig_patent_app_number] => 690631
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/690631 | Method and apparatus for measuring the offset voltages of SRAM sense amplifiers | Jul 29, 1996 | Issued |
Array
(
[id] => 3796406
[patent_doc_number] => 05841297
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Circuit arrangement for driving an MOS field-effect transistor allocated to the supply circuit of an electrical load'
[patent_app_type] => 1
[patent_app_number] => 8/684900
[patent_app_country] => US
[patent_app_date] => 1996-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5152
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841297.pdf
[firstpage_image] =>[orig_patent_app_number] => 684900
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/684900 | Circuit arrangement for driving an MOS field-effect transistor allocated to the supply circuit of an electrical load | Jul 24, 1996 | Issued |
Array
(
[id] => 3739331
[patent_doc_number] => 05703829
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Synchronous type semiconductor memory device which can be adapted to high frequency system clock signal'
[patent_app_type] => 1
[patent_app_number] => 8/681428
[patent_app_country] => US
[patent_app_date] => 1996-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 11581
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/703/05703829.pdf
[firstpage_image] =>[orig_patent_app_number] => 681428
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/681428 | Synchronous type semiconductor memory device which can be adapted to high frequency system clock signal | Jul 22, 1996 | Issued |
Array
(
[id] => 3790183
[patent_doc_number] => 05757711
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Amplifier circuit and complementary amplifier circuit with limiting function for output lower limit'
[patent_app_type] => 1
[patent_app_number] => 8/681431
[patent_app_country] => US
[patent_app_date] => 1996-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 7664
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/757/05757711.pdf
[firstpage_image] =>[orig_patent_app_number] => 681431
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/681431 | Amplifier circuit and complementary amplifier circuit with limiting function for output lower limit | Jul 22, 1996 | Issued |
Array
(
[id] => 3882249
[patent_doc_number] => 05825207
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Output buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/684588
[patent_app_country] => US
[patent_app_date] => 1996-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2217
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825207.pdf
[firstpage_image] =>[orig_patent_app_number] => 684588
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/684588 | Output buffer circuit | Jul 18, 1996 | Issued |
Array
(
[id] => 3798551
[patent_doc_number] => 05737268
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Modulated slope signal generation circuit, particularly for latch data sensing arrangements'
[patent_app_type] => 1
[patent_app_number] => 8/684431
[patent_app_country] => US
[patent_app_date] => 1996-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 4159
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/737/05737268.pdf
[firstpage_image] =>[orig_patent_app_number] => 684431
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/684431 | Modulated slope signal generation circuit, particularly for latch data sensing arrangements | Jul 18, 1996 | Issued |
Array
(
[id] => 3791185
[patent_doc_number] => 05821778
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Using cascode transistors having low threshold voltages'
[patent_app_type] => 1
[patent_app_number] => 8/683996
[patent_app_country] => US
[patent_app_date] => 1996-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 34
[patent_no_of_words] => 30781
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 312
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/821/05821778.pdf
[firstpage_image] =>[orig_patent_app_number] => 683996
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/683996 | Using cascode transistors having low threshold voltages | Jul 18, 1996 | Issued |
Array
(
[id] => 3804380
[patent_doc_number] => 05726929
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'Semiconductor storage device'
[patent_app_type] => 1
[patent_app_number] => 8/674827
[patent_app_country] => US
[patent_app_date] => 1996-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 30
[patent_no_of_words] => 18702
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 290
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/726/05726929.pdf
[firstpage_image] =>[orig_patent_app_number] => 674827
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/674827 | Semiconductor storage device | Jul 1, 1996 | Issued |
Array
(
[id] => 3738420
[patent_doc_number] => 05671175
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Capacitor over bitline DRAM cell'
[patent_app_type] => 1
[patent_app_number] => 8/670079
[patent_app_country] => US
[patent_app_date] => 1996-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 2545
[patent_no_of_claims] => 16
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[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/671/05671175.pdf
[firstpage_image] =>[orig_patent_app_number] => 670079
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/670079 | Capacitor over bitline DRAM cell | Jun 25, 1996 | Issued |
Array
(
[id] => 3753158
[patent_doc_number] => 05754468
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Compact multiport static random access memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/673732
[patent_app_country] => US
[patent_app_date] => 1996-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754468.pdf
[firstpage_image] =>[orig_patent_app_number] => 673732
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/673732 | Compact multiport static random access memory cell | Jun 25, 1996 | Issued |
Array
(
[id] => 3741987
[patent_doc_number] => 05694362
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Method and apparatus for high speed comparison'
[patent_app_type] => 1
[patent_app_number] => 8/668880
[patent_app_country] => US
[patent_app_date] => 1996-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3962
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/694/05694362.pdf
[firstpage_image] =>[orig_patent_app_number] => 668880
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/668880 | Method and apparatus for high speed comparison | Jun 23, 1996 | Issued |
Array
(
[id] => 3733040
[patent_doc_number] => 05673222
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-30
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/666979
[patent_app_country] => US
[patent_app_date] => 1996-06-20
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/673/05673222.pdf
[firstpage_image] =>[orig_patent_app_number] => 666979
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/666979 | Nonvolatile semiconductor memory device | Jun 19, 1996 | Issued |
Array
(
[id] => 3795118
[patent_doc_number] => 05822051
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Line amplifier for static RAM memory'
[patent_app_type] => 1
[patent_app_number] => 8/665631
[patent_app_country] => US
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[pdf_file] => patents/05/822/05822051.pdf
[firstpage_image] =>[orig_patent_app_number] => 665631
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665631 | Line amplifier for static RAM memory | Jun 17, 1996 | Issued |
Array
(
[id] => 3563283
[patent_doc_number] => 05574698
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver'
[patent_app_type] => 1
[patent_app_number] => 8/665621
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/574/05574698.pdf
[firstpage_image] =>[orig_patent_app_number] => 665621
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665621 | Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver | Jun 17, 1996 | Issued |
Array
(
[id] => 3804428
[patent_doc_number] => 05726932
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'Trench free SRAM cell structure'
[patent_app_type] => 1
[patent_app_number] => 8/663577
[patent_app_country] => US
[patent_app_date] => 1996-06-13
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/726/05726932.pdf
[firstpage_image] =>[orig_patent_app_number] => 663577
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/663577 | Trench free SRAM cell structure | Jun 12, 1996 | Issued |