Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17469994 [patent_doc_number] => 11276476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-15 [patent_title] => Common-mode comparison based fuse-readout circuit [patent_app_type] => utility [patent_app_number] => 17/117877 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117877 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117877
Common-mode comparison based fuse-readout circuit Dec 9, 2020 Issued
Array ( [id] => 17500426 [patent_doc_number] => 11289135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Precharge timing control [patent_app_type] => utility [patent_app_number] => 17/115327 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115327 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115327
Precharge timing control Dec 7, 2020 Issued
Array ( [id] => 17660449 [patent_doc_number] => 20220180914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => APPARATUSES AND METHODS FOR PROVIDING POWER RESPONSIVE TO INTERNAL POWER USAGE [patent_app_type] => utility [patent_app_number] => 17/114338 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114338
Apparatuses and methods for providing power responsive to internal power usage Dec 6, 2020 Issued
Array ( [id] => 18000717 [patent_doc_number] => 11501828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Apparatuses, memories, and methods for address decoding and selecting an access line [patent_app_type] => utility [patent_app_number] => 17/107639 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5476 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107639
Apparatuses, memories, and methods for address decoding and selecting an access line Nov 29, 2020 Issued
Array ( [id] => 16715383 [patent_doc_number] => 20210082530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/107317 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107317
Semiconductor memory device and operating method thereof Nov 29, 2020 Issued
Array ( [id] => 17516638 [patent_doc_number] => 11295797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Techniques to mitigate asymmetric long delay stress [patent_app_type] => utility [patent_app_number] => 17/103552 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13924 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103552
Techniques to mitigate asymmetric long delay stress Nov 23, 2020 Issued
Array ( [id] => 17380883 [patent_doc_number] => 11238904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => Using embedded switches for reducing capacitive loading on a memory system [patent_app_type] => utility [patent_app_number] => 17/103767 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103767 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103767
Using embedded switches for reducing capacitive loading on a memory system Nov 23, 2020 Issued
Array ( [id] => 16850342 [patent_doc_number] => 20210151087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => APPARATUSES AND METHODS FOR CLOCK LEVELING IN SEMICONDUCTOR MEMORIES [patent_app_type] => utility [patent_app_number] => 17/097717 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097717
Apparatuses and methods for clock leveling in semiconductor memories Nov 12, 2020 Issued
Array ( [id] => 17908398 [patent_doc_number] => 11462258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Memory device and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/097849 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5750 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097849
Memory device and operation method thereof Nov 12, 2020 Issued
Array ( [id] => 18000710 [patent_doc_number] => 11501821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same [patent_app_type] => utility [patent_app_number] => 17/090080 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 38 [patent_no_of_words] => 17886 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/090080
Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same Nov 4, 2020 Issued
Array ( [id] => 17757959 [patent_doc_number] => 11398257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Header layout design including backside power rail [patent_app_type] => utility [patent_app_number] => 17/085067 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085067
Header layout design including backside power rail Oct 29, 2020 Issued
Array ( [id] => 17224481 [patent_doc_number] => 11176991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Compute-in-memory (CIM) employing low-power CIM circuits employing static random access memory (SRAM) bit cells, particularly for multiply-and-accumluate (MAC) operations [patent_app_type] => utility [patent_app_number] => 17/084779 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15899 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084779
Compute-in-memory (CIM) employing low-power CIM circuits employing static random access memory (SRAM) bit cells, particularly for multiply-and-accumluate (MAC) operations Oct 29, 2020 Issued
Array ( [id] => 17332238 [patent_doc_number] => 11222706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods [patent_app_type] => utility [patent_app_number] => 17/075002 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075002
One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods Oct 19, 2020 Issued
Array ( [id] => 17332238 [patent_doc_number] => 11222706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods [patent_app_type] => utility [patent_app_number] => 17/075002 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075002
One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods Oct 19, 2020 Issued
Array ( [id] => 17332238 [patent_doc_number] => 11222706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods [patent_app_type] => utility [patent_app_number] => 17/075002 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075002
One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods Oct 19, 2020 Issued
Array ( [id] => 17332238 [patent_doc_number] => 11222706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods [patent_app_type] => utility [patent_app_number] => 17/075002 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075002
One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods Oct 19, 2020 Issued
Array ( [id] => 18721247 [patent_doc_number] => 11798599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Efficient placement of memory [patent_app_type] => utility [patent_app_number] => 17/763813 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5190 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17763813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/763813
Efficient placement of memory Oct 14, 2020 Issued
Array ( [id] => 17438755 [patent_doc_number] => 11264095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Electronic device and method of operating memory cell in the electronic device [patent_app_type] => utility [patent_app_number] => 17/039480 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10122 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039480
Electronic device and method of operating memory cell in the electronic device Sep 29, 2020 Issued
Array ( [id] => 17507657 [patent_doc_number] => 20220100760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => ACCELERATION OF DATA QUERIES IN MEMORY [patent_app_type] => utility [patent_app_number] => 17/033332 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033332 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033332
Acceleration of data queries in memory Sep 24, 2020 Issued
Array ( [id] => 17332229 [patent_doc_number] => 11222697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Three-dimensional nonvolatile memory and method of performing read operation in the nonvolatile memory [patent_app_type] => utility [patent_app_number] => 17/023002 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023002
Three-dimensional nonvolatile memory and method of performing read operation in the nonvolatile memory Sep 15, 2020 Issued
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